From: Matthijs Kooijman <matthijs@stdin.nl>
Date: Wed, 9 Sep 2009 17:56:28 +0000 (+0200)
Subject: Add a brainstorm for an outline.
X-Git-Tag: final-thesis~261
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=c8b72a250403339e3782e3efebc02a11f2411182;p=matthijs%2Fmaster-project%2Freport.git

Add a brainstorm for an outline.
---

diff --git a/Outline b/Outline
new file mode 100644
index 0000000..73246f9
--- /dev/null
+++ b/Outline
@@ -0,0 +1,41 @@
+Implementation issues
+
+State
+
+Prototype
+	Stages (-> Core, Normalization, -> VHDL)
+
+Core
+
+VHDL vs EDIF generation
+
+Normalization
+	Normal form
+	Rules used
+	Completeness / conditions on input
+	Termination
+	Casts
+
+Context
+
+Other FHDLs
+
+VHDL / Verilog / EDIF etc.
+
+Advantages of clash / why clash?
+
+Haskell as hardware
+	Dependent types
+	Impossible things: Infinite recursion, higher order expressions
+
+Haskell language coverage / constraints
+	Recursion
+	Builtin types
+	Custom types (Sum types, product types)
+	Function types / higher order expressions
+
+Future work
+	Boilerplate reduction (State distribution & pipelining)
+	Recursion
+	Multiple time domains
+	Multiple cycle descriptions