From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Tue, 23 Jun 2009 12:54:24 +0000 (+0200)
Subject: Ignore cast expressions when generating VHDL.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=c38002cdfd1ec55ffcd6661d7ac2d6c44d220d87;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Ignore cast expressions when generating VHDL.
---

diff --git a/VHDL.hs b/VHDL.hs
index eb45420..b2d5b30 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -264,6 +264,11 @@ mkConcSm ::
   (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
   -> VHDLState [AST.ConcSm] -- ^ The corresponding VHDL component instantiations.
 
+
+-- Ignore Cast expressions, they should not longer have any meaning as long as
+-- the type works out.
+mkConcSm (bndr, Cast expr ty) = mkConcSm (bndr, expr)
+
 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
   let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
   let valargs' = filter isValArg args