From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Tue, 23 Jun 2009 12:54:24 +0000 (+0200)
Subject: Ignore cast expressions when generating VHDL.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=c38002cdfd1ec55ffcd6661d7ac2d6c44d220d87;hp=c38002cdfd1ec55ffcd6661d7ac2d6c44d220d87;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Ignore cast expressions when generating VHDL.
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