From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Thu, 2 Jul 2009 14:47:18 +0000 (+0200)
Subject: Merge git://github.com/darchon/clash into cλash
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=c2f45d330f40225e7e5a1b6606665a16c2883d41;hp=f5f6d286f56ee1e822ece0258039ba2d2ce920aa;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Merge git://github.com/darchon/clash into cλash

* git://github.com/darchon/clash:
  We now output VHDL types in the correct order
  Removed the need for a special vector-type map.
  Added builtin functions: concat, reverse, iterate, iteraten, generate and generaten
---

diff --git a/Normalize.hs b/Normalize.hs
index e0591a8..0004ee3 100644
--- a/Normalize.hs
+++ b/Normalize.hs
@@ -213,6 +213,7 @@ casewild expr@(Case scrut b ty alts) = do
       -- and binds that to b.
       mkextracts :: CoreBndr -> Int -> TransformMonad (Maybe (CoreBndr, CoreExpr))
       mkextracts b i =
+        -- TODO: Use free variables instead of is_wild. is_wild is a hack.
         if is_wild b || Type.isFunTy (Id.idType b) 
           -- Don't create extra bindings for binders that are already wild, or
           -- for binders that bind function types (to prevent loops with