From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Tue, 23 Jun 2009 10:53:47 +0000 (+0200)
Subject: Always add a clk port map on instantiations.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=b4b8def2facb3d3bf92ee02a499405efdf986324;hp=b4b8def2facb3d3bf92ee02a499405efdf986324;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Always add a clk port map on instantiations.

This changes make the translator generate synthesizable VHDL again.
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