From: Christiaan Baaij Date: Mon, 31 Aug 2009 19:55:21 +0000 (+0200) Subject: Hopefully finalized presentation X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=b4b0e8a2e09609f70bc5ed0fb69a8d966e4a6813;p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git Hopefully finalized presentation --- diff --git a/PolyAlu.lhs b/PolyAlu.lhs index c0d196d..a4dc6e1 100644 --- a/PolyAlu.lhs +++ b/PolyAlu.lhs @@ -21,6 +21,7 @@ import qualified Prelude as P \includegraphics[width=4.75cm]{simpleCPU} \end{figure} \column{0.5\textwidth} +\vspace{5em} \begin{itemize} \item Polymorphic, Higher-Order CPU \item Use of state will be simple @@ -49,9 +50,10 @@ First we define some ALU types: \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} type Op a = a -> a -> a +type Opcode = Bit \end{code} \end{beamercolorbox}\pause -\vspace{2.5em} +\vspace{1em} And some Register types: \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} @@ -68,7 +70,8 @@ type Word = SizedInt D12 %endif \end{columns} }\note[itemize]{ -\item The first type is already polymorphic in input / output type +\item The ALU operation is already polymorphic in input / output type +\item We use a fixed size vector as the placeholder for the registers \item State has to be of the State type to be recognized as such } @@ -82,7 +85,6 @@ type Word = SizedInt D12 Abstract ALU definition: \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} -type Opcode = Bit alu :: Op a -> Op a -> Opcode -> a -> a -> a @@ -92,7 +94,7 @@ alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-} a b = op2 a b \end{beamercolorbox} }\note[itemize]{ \item Alu is both higher-order, and polymorphic -\item Two parameters are "compile time", others are "runtime" +\item First two parameters are "compile time", other three are "runtime" \item We support pattern matching } @@ -121,10 +123,8 @@ registers data_in rdaddr wraddr (State mem) = \end{code} \end{beamercolorbox} }\note[itemize]{ -\item RangedWord runs from 0 to the upper bound -\item mem is statefull -\item We support guards -\item replace is a builtin function +\item mem is statefull, indicated by the 'State' type +\item replace and (!) are a builtin functions } \subsection{Simple CPU: ALU \& Register Bank} @@ -155,7 +155,7 @@ cpu (opc, d, rdaddr, wraddr) ram = (ram', alu_out) \end{itemize} }\note[itemize]{ \item We use the new Annotion functionality to indicate this is the top level. TopEntity is defined by us. -\item the primOp and vectOp frameworks are now supplied with real functionality, the plus (+) operations +\item At this stage, both operations for the ALU are defined \item No polymorphism or higher-order stuff is allowed at this level. \item Functions must be specialized, and have primitives for input and output } diff --git a/beamerinnerthemecaes.sty b/beamerinnerthemecaes.sty index 580fe3c..29126b7 100644 --- a/beamerinnerthemecaes.sty +++ b/beamerinnerthemecaes.sty @@ -60,7 +60,7 @@ \setbeamertemplate{title page} { \begin{centering} - \vfill + \vskip2em% \begin{beamercolorbox}[sep=8pt,center]{title} \usebeamerfont{title}\inserttitle\par% \ifx\insertsubtitle\@empty% diff --git a/demo.lhs b/demo.lhs index 61a5567..f50a959 100644 --- a/demo.lhs +++ b/demo.lhs @@ -3,6 +3,7 @@ \frame{ \frametitle{Demo} \begin{itemize} + \item Pre-Recored Video: VHDL Synthesis takes too long \item Simulate the CPU description \item Translate the CPU to VHDL \item Simulate the generated VHDL @@ -14,9 +15,9 @@ \frame{ \frametitle{Generated Schematic} \begin{figure} -\centerline{\includegraphics<1>[width=10cm]{cpucomplete} -\includegraphics<2>[width=10cm]{cpualu} -\includegraphics<3>[height=6cm]{cpuregisters}} +\centerline{\includegraphics<1>[width=10.3cm]{cpucomplete} +\includegraphics<2>[width=11.3cm]{cpualu} +\includegraphics<3>[height=6.3cm]{cpuregisters}} \end{figure} } diff --git a/howdoesitwork.lhs b/howdoesitwork.lhs index b9970d6..4c26ca5 100644 --- a/howdoesitwork.lhs +++ b/howdoesitwork.lhs @@ -14,7 +14,8 @@ \end{itemize} }\note[itemize]{ \item Here is a quick insight as to how WE translate Haskell to Hardware +\item Reduction rules are used to get a required normal form. \item Normal form already looks like hardware (components and lines) -\item You can also use TH, like ForSyDe. Or traverse datastructures, like ? +\item You can also use TH, like ForSyDe. Or traverse datastructures, like Lava? \item We're in luck with the GHC API update of 6.10 and onwards } diff --git a/introduction.lhs b/introduction.lhs index c7b0bca..939582f 100644 --- a/introduction.lhs +++ b/introduction.lhs @@ -18,29 +18,12 @@ \item \clash{} is currently meant for rapid prototyping, not verification of hardware designs \item Functional languages are close to Hardware \item We can only translate a subset of Haskell -\item All functions are descriptions of Mealy Machines +\item All functions are structural descriptions with a Mealy Machines perspective } -% \subsection{Mealy Machine} -% \frame -% { -% \frametitle{What is a Mealy Machine again?} -% \begin{figure} -% \centerline{\includegraphics[width=10cm]{mealymachine}} -% \label{img:mealymachine} -% \end{figure} -% } -% \note[itemize]{ -% \item Mealy machine bases its output on current input and previous state -% \item: TODO: Integrate this slide with the next two. First, show the picture -% with the mealyMachine type signature (and rename it to "func"). Then, show the -% run function, without type signature. Focus is on correspondence to the -% picture. -% } - \frame { -\frametitle{Haskell Description} +\frametitle{Mealy Machine} \begin{figure} \centerline{\includegraphics<1>[width=6.25cm]{mealymachine2} \includegraphics<2>[width=6.25cm]{mealymachine2-func-red} @@ -49,8 +32,8 @@ \end{figure} \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} -run func {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} [] = [] -run func {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} (i:inputs) = o:outputs +run {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} [] = [] +run {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} (i:inputs) = o:outputs where ({-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-}, o) = {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} i {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} outputs = run {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} {-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-} input @@ -58,8 +41,10 @@ run func {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} (i:inputs) = o:outputs \end{beamercolorbox} } \note[itemize]{ +\item A Mealy machine bases its output on the current state and the input \item State is part of the function signature -\item Both the current state, as the updated State +\item Both the current state, and the updated State +\item The run function simulates a mealy machine for the provided number of inputs } \frame @@ -77,3 +62,7 @@ func :: \end{code} \end{beamercolorbox} } +\note[itemize]{ +\item In \clash{} you describe the logic part of the mealy machine +\item The state in the signature is turned into memory elements when translating to VHDL +} diff --git a/reducer.lhs b/reducer.lhs index 03c688c..21baeeb 100644 --- a/reducer.lhs +++ b/reducer.lhs @@ -10,7 +10,7 @@ \column{0.5\textwidth} \begin{itemize} \item We implemented a reduction circuit in \clash{}\pause - \item Simulation results in Haskell match VHDL simulation results\pause + \item Simulated first Haskell. VHDL simulation results match\pause \item Synthesis completes without errors or warnings\pause \item Around half speed of handcoded and optimized VHDL \end{itemize} @@ -18,7 +18,9 @@ }\note[itemize]{ \item Toys like the poly cpu one are good to give a quick demo \item But we used \clash{} to design 'real' hardware -\item Reduction circuit sums the numbers in a row of a (sparse) matrix +\item Reduction circuit sums the numbers in a row, of different length +\item It uses a pipelined adder: multiple rows in pipeline, rows longer than pipeline +\item We hope you see this is not a trivial problem \item Nice speed considering we don't optimize for it (only single example!) } diff --git a/reducer.svg b/reducer.svg index 39152bc..96ce958 100644 --- a/reducer.svg +++ b/reducer.svg @@ -1,14 +1,79 @@ + width="325.10861" + height="279.28186" + id="svg2" + sodipodi:version="0.32" + inkscape:version="0.46" + sodipodi:docname="reducer.svg" + inkscape:output_extension="org.inkscape.output.svg.inkscape"> + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + - - + id="g5141" + transform="matrix(0,1,-1,0,510.99869,-50.573108)"> - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + style="fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + id="rect5119" + y="300.95374" + x="244.9467" + height="187.29399" + width="41.994167" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Input rows + + PipelinedAdder diff --git a/summary.lhs b/summary.lhs index 58feaa9..6467af8 100644 --- a/summary.lhs +++ b/summary.lhs @@ -5,8 +5,8 @@ \frametitle{Some final words} \begin{itemize} \item Still a lot to do: translate larger subset of Haskell - \item Real world prototypes can be made in \clash{} - \item \clash{} is another great example of how to bring functional expressivity to hardware designs + \item Real world prototype designs can already be made in \clash{} +% \item \clash{} is another great example of how to bring functional expressivity to hardware designs \end{itemize} } @@ -37,3 +37,30 @@ registers :: (RegState s a, a ) \end{code} } + +\frame +{ +\frametitle{Supported Functionality} +\begin{itemize} +\item Polymorphism +\item Higher Order Functions +\item Fixed-Size Vectors (Simulation) +\item Ranged and Sized Integers (Simulation) +\item Custom Datatypes +\item Booleans, Tuples +\item Pattern Matching +\item Guards +\end{itemize} +} + +\frame +{ +\frametitle{Unsupported Functionality} +\begin{itemize} +\item Recursions +\item Lists (Dynamic Length) +\item Standard Haskell Types: Integer, Char, etc. +\item Monads +\item And much much more... +\end{itemize} +}