From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Thu, 6 Aug 2009 15:08:25 +0000 (+0200)
Subject: Allow explicit empty VHDL types using Maybe.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=ad9bc80c39c42f645c76c65e1d3833148b854c1e;hp=ad9bc80c39c42f645c76c65e1d3833148b854c1e;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Allow explicit empty VHDL types using Maybe.

The VHDL type generating functions can now return "Nothing" to mean that an
empty type would be generated. There are still some spots (builtin
functions mostly) that should handle this more gracefully, but it works
for now. Only single-constructor zero-argument algebraic types generate
the empty type currently, e.g. ().
---