From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Mon, 2 Feb 2009 09:01:37 +0000 (+0100)
Subject: Write the resulting vhdl to file.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=a628d8d874df6af54c6d4f766012bac117eea037;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Write the resulting vhdl to file.
---

diff --git a/Translator.hs b/Translator.hs
index 11e425d..4992d1c 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -26,6 +26,7 @@ import qualified Monad
 -- ForSyDe to get access to these modules.
 import qualified ForSyDe.Backend.VHDL.AST as AST
 import qualified ForSyDe.Backend.VHDL.Ppr
+import qualified ForSyDe.Backend.VHDL.FileIO
 import qualified ForSyDe.Backend.Ppr
 -- This is needed for rendering the pretty printed VHDL
 import Text.PrettyPrint.HughesPJ (render)
@@ -49,6 +50,7 @@ main =
           -- Turn bind into VHDL
           let vhdl = State.evalState (mkVHDL binds) (VHDLSession 0 [])
           liftIO $ putStr $ render $ ForSyDe.Backend.Ppr.ppr vhdl
+          liftIO $ ForSyDe.Backend.VHDL.FileIO.writeDesignFile vhdl "../vhdl/vhdl/output.vhdl"
           return ()
   where
     -- Turns the given bind into VHDL