From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Thu, 9 Apr 2009 16:18:29 +0000 (+0200)
Subject: Translate the SizedWord type to a VHDL vector.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=a3ff46ea19a1966c2268fe99df24c15d04abc000;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Translate the SizedWord type to a VHDL vector.
---

diff --git a/VHDL.hs b/VHDL.hs
index 836f06b..1d605ea 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -33,7 +33,7 @@ import FlattenTypes
 import TranslatorTypes
 import HsValueMap
 import Pretty
-import HsTools
+import CoreTools
 
 createDesignFiles ::
   FlatFuncMap
@@ -370,6 +370,7 @@ vhdl_ty ty = do
             let name = Name.getOccString (TyCon.tyConName tycon)
             case name of
               "FSVec" -> Just $ mk_fsvec_ty ty args
+              "SizedWord" -> Just $ mk_vector_ty (sized_word_len ty) ty
               otherwise -> Nothing
       -- Return new_ty when a new type was successfully created
       Maybe.fromMaybe 
@@ -395,6 +396,23 @@ mk_fsvec_ty ty args = do
   State.modify (Map.insert (OrdType ty) (ty_id, ty_dec))
   return ty_id
 
+-- | Create a VHDL vector type
+mk_vector_ty ::
+  Int -- ^ The length of the vector
+  -> Type.Type -- ^ The Haskell type to create a VHDL type for
+  -> TypeState AST.TypeMark -- The typemark created.
+
+mk_vector_ty len ty = do
+  -- Assume there is a single type argument
+  let ty_id = mkVHDLExtId $ "vector_" ++ (show len)
+  -- TODO: Use el_ty
+  let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))]
+  let ty_def = AST.TDA $ AST.ConsArrayDef range std_logic_ty
+  let ty_dec = AST.TypeDec ty_id ty_def
+  -- TODO: Check name uniqueness
+  State.modify (Map.insert (OrdType ty) (ty_id, ty_dec))
+  return ty_id
+
 
 builtin_types = 
   Map.fromList [