From: Christiaan Baaij Date: Mon, 31 Aug 2009 20:55:35 +0000 (+0200) Subject: Fix typos X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=HEAD;p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git Fix typos --- diff --git a/PolyAlu.hs b/PolyAlu.hs index a464ffb..b9d0da8 100644 --- a/PolyAlu.hs +++ b/PolyAlu.hs @@ -5,27 +5,27 @@ module Main where import CLasH.HardwareTypes import CLasH.Translator.Annotations import qualified Prelude as P -{-# LINE 51 "PolyAlu.lhs" #-} +{-# LINE 52 "PolyAlu.lhs" #-} type Op a = a -> a -> a -{-# LINE 58 "PolyAlu.lhs" #-} +type Opcode = Bit +{-# LINE 60 "PolyAlu.lhs" #-} type RegBank s a = Vector (s :+: D1) a type RegState s a = State (RegBank s a) -{-# LINE 66 "PolyAlu.lhs" #-} +{-# LINE 68 "PolyAlu.lhs" #-} type Word = SizedInt D12 -{-# LINE 85 "PolyAlu.lhs" #-} -type Opcode = Bit +{-# LINE 88 "PolyAlu.lhs" #-} alu :: Op a -> Op a -> Opcode -> a -> a -> a alu op1 op2 Low a b = op1 a b alu op1 op2 High a b = op2 a b -{-# LINE 108 "PolyAlu.lhs" #-} +{-# LINE 110 "PolyAlu.lhs" #-} registers :: ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => a -> RangedWord s -> RangedWord s -> (RegState s a) -> (RegState s a, a ) -{-# LINE 116 "PolyAlu.lhs" #-} +{-# LINE 118 "PolyAlu.lhs" #-} registers data_in rdaddr wraddr (State mem) = ((State mem'), data_out) where diff --git a/reducer.lhs b/reducer.lhs index 21baeeb..061f9db 100644 --- a/reducer.lhs +++ b/reducer.lhs @@ -10,7 +10,7 @@ \column{0.5\textwidth} \begin{itemize} \item We implemented a reduction circuit in \clash{}\pause - \item Simulated first Haskell. VHDL simulation results match\pause + \item Simulated in Haskell. VHDL simulation results match\pause \item Synthesis completes without errors or warnings\pause \item Around half speed of handcoded and optimized VHDL \end{itemize}