From: christiaanb <christiaan.baaij@gmail.com>
Date: Thu, 17 Jun 2010 08:26:44 +0000 (+0200)
Subject: Fix vhdl type generation of index type, as upper bound is now exclusive
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=98f12a87ff98c614f678ee71a895066de072a069;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Fix vhdl type generation of index type, as upper bound is now exclusive
---

diff --git a/clash/CLasH/VHDL/VHDLTools.hs b/clash/CLasH/VHDL/VHDLTools.hs
index a70036e..8cb2f5e 100644
--- a/clash/CLasH/VHDL/VHDLTools.hs
+++ b/clash/CLasH/VHDL/VHDLTools.hs
@@ -346,7 +346,8 @@ mkHTypeEither' ty | ty_has_free_tyvars ty = return $ Left $ "\nVHDLTools.mkHType
                   return $ Right $ SizedIType len
                 "Index" -> do
                   bound <- tfp_to_int (ranged_word_bound_ty ty)
-                  return $ Right $ RangedWType bound
+                  -- Upperbound is exclusive, hence the -1
+                  return $ Right $ RangedWType (bound - 1)
                 otherwise ->
                   mkTyConHType tycon args
     Nothing -> return $ Left $ "\nVHDLTools.mkHTypeEither': Do not know what to do with type: " ++ pprString ty