From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Thu, 29 Jan 2009 14:26:35 +0000 (+0100)
Subject: Rework the VHDL generation to be more bottom up.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=9249dab48240dbc07f1c6b72723a13bdc3a55663;hp=9249dab48240dbc07f1c6b72723a13bdc3a55663;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Rework the VHDL generation to be more bottom up.

The new function expandExpr does something similar to getInstantiations
(and is used instead of it now), but follows a more bottom up approach,
generating new signals as needed and only connecting these signals to
ports at the very end. This allows for more general handling of nested
expressions and will probably make things less complex.

For now, this means that the Translator can only translate the trivial
"wire" hardware model, more support coming up.

This also means that we're using VHDLId's in almost all SignalNameMaps
now, which reduced the conversion from String.
---