From: Christiaan Baaij <christiaan.baaij@gmail.com>
Date: Mon, 13 Jul 2009 10:01:00 +0000 (+0200)
Subject: Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=83a9910bd8031fbce225992e432e7dfba73b5c0f;hp=46f93616d6a7ef012c5f07698d56372881196015;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Merge branch 'cλash' of git.stderr.nl/matthijs/projects/master-project

* 'cλash' of http://git.stderr.nl/matthijs/projects/master-project:
  Generate proper VHDL for top level bindings with no arguments.
  Use is_local_var for limiting appsimpl and letsimpl.
  Add newline at the end of file.
  Add is_local_var predicate.
  Santize comment dashes position.
  Normalize all used global binders.
---

diff --git a/CoreTools.hs b/CoreTools.hs
index bd6f329..3bfe1a1 100644
--- a/CoreTools.hs
+++ b/CoreTools.hs
@@ -38,9 +38,10 @@ import Pretty
 
 -- | Evaluate a core Type representing type level int from the tfp
 -- library to a real int.
-eval_tfp_int :: Type.Type -> Int
-eval_tfp_int ty =
+eval_tfp_int :: HscTypes.HscEnv -> Type.Type -> Int
+eval_tfp_int env ty =
   unsafeRunGhc $ do
+    GHC.setSession env
     -- Automatically import modules for any fully qualified identifiers
     setDynFlag DynFlags.Opt_ImplicitImportQualified
 
diff --git a/VHDLTools.hs b/VHDLTools.hs
index 1e6e5bc..e7c598d 100644
--- a/VHDLTools.hs
+++ b/VHDLTools.hs
@@ -473,9 +473,8 @@ mkHType ty = do
               case elem_htype_either of
                 -- Could create element type
                 Right elem_htype -> do
-                  env <- getA vsHscEnv
-                  let norm_ty = normalise_tfp_int env (tfvec_len_ty ty)
-                  return $ Right $ VecType (OrdType norm_ty) elem_htype
+                  len <- tfp_to_int (tfvec_len_ty ty)
+                  return $ Right $ VecType len elem_htype
                 -- Could not create element type
                 Left err -> return $ Left $ 
                   "VHDLTools.mkHType: Can not construct vectortype for elementtype: " ++ pprString el_ty  ++ "\n"
@@ -527,10 +526,12 @@ isReprType ty = do
 tfp_to_int :: Type.Type -> TypeSession Int
 tfp_to_int ty = do
   lens <- getA vsTfpInts
-  let existing_len = Map.lookup (OrdType ty) lens
+  hscenv <- getA vsHscEnv
+  let norm_ty = normalise_tfp_int hscenv ty
+  let existing_len = Map.lookup (OrdType norm_ty) lens
   case existing_len of
     Just len -> return len
     Nothing -> do
-      let new_len = eval_tfp_int ty
-      modA vsTfpInts (Map.insert (OrdType ty) (new_len))
+      let new_len = eval_tfp_int hscenv ty
+      modA vsTfpInts (Map.insert (OrdType norm_ty) (new_len))
       return new_len
\ No newline at end of file
diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index b4c1d69..5562c6a 100644
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -41,7 +41,7 @@ instance Ord OrdType where
 
 data HType = StdType OrdType |
              ADTType String [HType] |
-             VecType OrdType HType |
+             VecType Int HType |
              SizedWType Int |
              RangedWType Int |
              SizedIType Int |