From: Christiaan Baaij <christiaan.baaij@gmail.com>
Date: Mon, 13 Jul 2009 10:01:00 +0000 (+0200)
Subject: Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=83a9910bd8031fbce225992e432e7dfba73b5c0f;hp=-c;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Merge branch 'cλash' of git.stderr.nl/matthijs/projects/master-project

* 'cλash' of http://git.stderr.nl/matthijs/projects/master-project:
  Generate proper VHDL for top level bindings with no arguments.
  Use is_local_var for limiting appsimpl and letsimpl.
  Add newline at the end of file.
  Add is_local_var predicate.
  Santize comment dashes position.
  Normalize all used global binders.
---

83a9910bd8031fbce225992e432e7dfba73b5c0f
diff --combined CoreTools.hs
index 9888255,bd6f329..3bfe1a1
--- a/CoreTools.hs
+++ b/CoreTools.hs
@@@ -38,10 -38,9 +38,10 @@@ import Prett
  
  -- | Evaluate a core Type representing type level int from the tfp
  -- library to a real int.
 -eval_tfp_int :: Type.Type -> Int
 -eval_tfp_int ty =
 +eval_tfp_int :: HscTypes.HscEnv -> Type.Type -> Int
 +eval_tfp_int env ty =
    unsafeRunGhc $ do
 +    GHC.setSession env
      -- Automatically import modules for any fully qualified identifiers
      setDynFlag DynFlags.Opt_ImplicitImportQualified
  
@@@ -223,4 -222,4 +223,4 @@@ getLiterals :: CoreSyn.CoreExpr -> [Cor
  getLiterals app@(CoreSyn.App _ _) = literals
    where
      (CoreSyn.Var f, args) = CoreSyn.collectArgs app
-     literals = filter (is_lit) args
+     literals = filter (is_lit) args