From: christiaanb Date: Thu, 17 Jun 2010 08:30:57 +0000 (+0200) Subject: Implement API change of shiftl and shiftr, limit Prelude import of HardwareTypes X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=7f6a8f38eea6aec322fad713d9b8dd67ffd0a9de;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Implement API change of shiftl and shiftr, limit Prelude import of HardwareTypes --- diff --git a/clash/CLasH/HardwareTypes.hs b/clash/CLasH/HardwareTypes.hs index d66befe..dbb0eca 100644 --- a/clash/CLasH/HardwareTypes.hs +++ b/clash/CLasH/HardwareTypes.hs @@ -1,4 +1,4 @@ -{-# LANGUAGE TemplateHaskell, DeriveDataTypeable, FlexibleContexts, TypeFamilies, TypeOperators #-} +{-# LANGUAGE TemplateHaskell, DeriveDataTypeable #-} module CLasH.HardwareTypes ( module Types @@ -9,8 +9,6 @@ module CLasH.HardwareTypes , module Prelude , Bit(..) , State(..) - , resizeInt - , resizeWord , hwand , hwor , hwxor @@ -21,31 +19,21 @@ module CLasH.HardwareTypes ) where import qualified Prelude as P -import Prelude hiding ( - null, length, head, tail, last, init, take, drop, (++), map, foldl, foldr, - zipWith, zip, unzip, concat, reverse, iterate ) +import Prelude (Bool(..),Num(..),Eq(..),Ord(..),snd,fst,otherwise,(&&),(||),not) import Types import Data.Param.Vector import Data.Param.Index -import qualified Data.Param.Signed as Signed -import Data.Param.Signed hiding (resize) -import qualified Data.Param.Unsigned as Unsigned -import Data.Param.Unsigned hiding (resize) +import Data.Param.Signed +import Data.Param.Unsigned import Language.Haskell.TH.Lift import Data.Typeable newtype State s = State s deriving (P.Show) -resizeInt :: (NaturalT nT, NaturalT nT') => Signed nT -> Signed nT' -resizeInt = Signed.resize - -resizeWord :: (NaturalT nT, NaturalT nT') => Unsigned nT -> Unsigned nT' -resizeWord = Unsigned.resize - -- The plain Bit type data Bit = High | Low - deriving (P.Show, P.Eq, P.Read, Typeable) + deriving (P.Show, Eq, P.Read, Typeable) deriveLift ''Bit diff --git a/clash/CLasH/VHDL/Constants.hs b/clash/CLasH/VHDL/Constants.hs index c70ca71..23ac95d 100644 --- a/clash/CLasH/VHDL/Constants.hs +++ b/clash/CLasH/VHDL/Constants.hs @@ -155,11 +155,11 @@ dropId = "drop" -- | shiftl function identifier shiftlId :: String -shiftlId = "shiftl" +shiftlId = "shiftIntoL" -- | shiftr function identifier shiftrId :: String -shiftrId = "shiftr" +shiftrId = "shiftIntoR" -- | rotl function identifier rotlId :: String diff --git a/clash/Data/Param/Signed.hs b/clash/Data/Param/Signed.hs index 26ac677..e85fe60 100644 --- a/clash/Data/Param/Signed.hs +++ b/clash/Data/Param/Signed.hs @@ -1,7 +1,7 @@ {-# LANGUAGE TypeFamilies, TypeOperators, ScopedTypeVariables, FlexibleInstances, TemplateHaskell, Rank2Types, FlexibleContexts #-} module Data.Param.Signed ( Signed - , resize + , resizeSigned ) where import Language.Haskell.TH @@ -18,8 +18,8 @@ instance NaturalT nT => Lift (Signed nT) where decSignedT :: Integer -> Q Type decSignedT n = appT (conT (''Signed)) (decLiteralT n) -resize :: (NaturalT nT, NaturalT nT') => Signed nT -> Signed nT' -resize a = fromInteger (toInteger a) +resizeSigned :: (NaturalT nT, NaturalT nT') => Signed nT -> Signed nT' +resizeSigned a = fromInteger (toInteger a) sizeT :: Signed nT -> nT diff --git a/clash/Data/Param/Unsigned.hs b/clash/Data/Param/Unsigned.hs index aae032d..6f06dbd 100644 --- a/clash/Data/Param/Unsigned.hs +++ b/clash/Data/Param/Unsigned.hs @@ -1,7 +1,7 @@ {-# LANGUAGE TypeFamilies, TypeOperators, ScopedTypeVariables, FlexibleInstances, TemplateHaskell, Rank2Types, FlexibleContexts #-} module Data.Param.Unsigned ( Unsigned - , resize + , resizeUnsigned , fromIndex ) where @@ -27,8 +27,8 @@ fromIndex :: ) => Index nT -> Unsigned nT' fromIndex index = Unsigned (toInteger index) -resize :: (NaturalT nT, NaturalT nT') => Unsigned nT -> Unsigned nT' -resize a = fromInteger (toInteger a) +resizeUnsigned :: (NaturalT nT, NaturalT nT') => Unsigned nT -> Unsigned nT' +resizeUnsigned a = fromInteger (toInteger a) sizeT :: Unsigned nT -> nT diff --git a/clash/Data/Param/Vector.hs b/clash/Data/Param/Vector.hs index 6f5b722..f726945 100644 --- a/clash/Data/Param/Vector.hs +++ b/clash/Data/Param/Vector.hs @@ -28,8 +28,8 @@ module Data.Param.Vector , foldr , zip , unzip - , shiftl - , shiftr + , shiftIntoL + , shiftIntoR , rotl , rotr , concat @@ -179,13 +179,13 @@ zip = liftV2 P.zip unzip :: Vector s (a, b) -> (Vector s a, Vector s b) unzip (Vector xs) = let (a,b) = P.unzip xs in (Vector a, Vector b) -shiftl :: (PositiveT s, NaturalT n, n ~ Pred s, s ~ Succ n) => - Vector s a -> a -> Vector s a -shiftl xs x = x +> init xs +shiftIntoL :: (PositiveT s, NaturalT n, n ~ Pred s, s ~ Succ n) => + Vector s a -> a -> Vector s a +shiftIntoL xs x = x +> init xs -shiftr :: (PositiveT s, NaturalT n, n ~ Pred s, s ~ Succ n) => - Vector s a -> a -> Vector s a -shiftr xs x = tail xs <+ x +shiftIntoR :: (PositiveT s, NaturalT n, n ~ Pred s, s ~ Succ n) => + Vector s a -> a -> Vector s a +shiftIntoR xs x = tail xs <+ x rotl :: forall s a . NaturalT s => Vector s a -> Vector s a rotl = liftV rotl' diff --git a/clash/clash.cabal b/clash/clash.cabal index 9a62eac..5f8efea 100644 --- a/clash/clash.cabal +++ b/clash/clash.cabal @@ -1,5 +1,5 @@ name: clash -version: 0.1.0.3 +version: 0.1.1.0 build-type: Simple synopsis: CAES Language for Synchronous Hardware (CLaSH) description: CLaSH is a tool-chain/language to translate subsets of diff --git a/reducer.hs b/reducer.hs index 39e136f..a4d4bbb 100644 --- a/reducer.hs +++ b/reducer.hs @@ -3,7 +3,7 @@ module Reducer where import qualified Prelude as P -import CLasH.HardwareTypes hiding ((>>)) +import CLasH.HardwareTypes import CLasH.Translator.Annotations -- ======================================= @@ -48,8 +48,8 @@ notValid = (False, (0, 0)) -- ==================== -- = Helper functions = -- ==================== -v << e = shiftr v e -e >> v = shiftl v e +v <<+ e = shiftIntoR v e +e +>> v = shiftIntoL v e -- ======================= -- = Reducer State types = @@ -133,15 +133,15 @@ rippleBuffer :: rippleBuffer (State buf) (inp, shift) = (State buf', out1, out2) where -- Write value - next_valids = (map (\(a, b) -> a) buf) << True + next_valids = (map (\(a, b) -> a) buf) <<+ True buf'' = zipWith selects buf next_valids selects cell next_valid = if (not (fst cell)) && next_valid then (True, inp) else cell -- Shift values - buf' | shift == 2 = (False, 0) >> ((False, 0) >> buf'') - | shift == 1 = (False, 0) >> buf'' + buf' | shift == 2 = (False, 0) +>> ((False, 0) +>> buf'') + | shift == 1 = (False, 0) +>> buf'' | otherwise = buf'' -- Read values out1 = last buf @@ -185,7 +185,7 @@ fpAdder (State ((buffer, pipe), adderState)) (arg1, arg2) = (State ((buffer', pi -- placeholder adder (adderState', adderOut) = fpPlaceholder adderState (a1, a2) -- Save corresponding indexes and valid bits - pipe' = (valid arg1, discr arg1) >> pipe + pipe' = (valid arg1, discr arg1) +>> pipe -- Produce output for time T and T+1 pipeEndT = last pipe pipeEndT_1 = last (init pipe) @@ -280,10 +280,10 @@ reducer (State (Reducer {..})) (data_in, index) = ( State Reducer { discrState valT_1 | discr pipeT == discr pipeT_1 = not (valid from_res_mem) | otherwise = valid from_res_mem (discrO, valT, inPipe , outPipe) = pipeline - pipeline' = ( (discrN, index, new_discr) >> discrO + pipeline' = ( (discrN, index, new_discr) +>> discrO , valT_1 - , (data_in, index) >> inPipe - , output' >> outPipe + , (data_in, index) +>> inPipe + , output' +>> outPipe ) @@ -356,13 +356,13 @@ runReducer = ( reduceroutput input = siminput istate = initstate output = run reducer istate input - reduceroutput = P.map fst (filter (\x -> (snd x)) output) + reduceroutput = P.map fst (P.filter (\x -> (snd x)) output) validoutput = [P.foldl (+) 0 - (P.map (\z -> toInteger (fst z)) - (filter (\x -> (snd x) == i) input)) | i <- [0..30]] - equal = [validoutput!!i == toInteger (fst (reduceroutput!!i)) | + (P.map (\z -> P.toInteger (fst z)) + (P.filter (\x -> (snd x) == i) input)) | i <- [0..30]] + equal = [validoutput P.!! i == P.toInteger (fst (reduceroutput P.!! i)) | i <- [0..30]] - allEqual = foldl1 (&&) equal + allEqual = P.foldl1 (&&) equal siminput :: [(DataInt, ArrayIndex)] siminput = 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