From: Matthijs Kooijman Date: Fri, 13 Feb 2009 14:12:21 +0000 (+0100) Subject: Generate dummy component instantiations for each architecture. X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=7ab181699998f86de0a079ec7a63f7e61ec95cb9;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Generate dummy component instantiations for each architecture. We don't have a session available, so we can't lookup or generate any names yet. Also, the portmaps are not implemented yet. --- diff --git a/VHDL.hs b/VHDL.hs index 8c2fe03..6b8b7b6 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -102,13 +102,16 @@ createArchitecture hsfunc fdata = sigs = flat_sigs flatfunc args = flat_args flatfunc res = flat_res flatfunc + apps = flat_apps flatfunc entity_id = Maybe.fromMaybe (error $ "Building architecture without an entity? This should not happen!") (getEntityId fdata) -- Create signal declarations for all signals that are not in args and -- res sig_decs = [mkSigDec info | (id, info) <- sigs, (all (id `Foldable.notElem`) (res:args)) ] - arch = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) [] + -- Create component instantiations for all function applications + insts = map (AST.CSISm . mkCompInsSm) apps + arch = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) insts in fdata { funcArch = Just arch } @@ -120,7 +123,19 @@ mkSigDec info = (error $ "Unnamed signal? This should not happen!") (sigName info) ty = sigTy info - + +-- | Transforms a flat function application to a VHDL component instantiation. +mkCompInsSm :: + FApp UnnamedSignal -- | The application to look at. + -> AST.CompInsSm -- | The corresponding VHDL component instantiation. + +mkCompInsSm app = + AST.CompInsSm label (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps) + where + entity_id = mkVHDLId "foo" + label = mkVHDLId "app" + portmaps = [] + -- | Extracts the generated entity id from the given funcdata getEntityId :: FuncData -> Maybe AST.VHDLId getEntityId fdata =