From: Matthijs Kooijman Date: Wed, 18 Feb 2009 18:38:10 +0000 (+0100) Subject: Generate VHDL for UncondDefs. X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=6a1062010dabf7631e555d2eb9f90fa571f5d34d;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Generate VHDL for UncondDefs. --- diff --git a/VHDL.hs b/VHDL.hs index c791a34..adf1bf9 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -192,6 +192,14 @@ mkConcSm sigs (FApp hsfunc args res) = do let portmaps = mkAssocElems sigs args res entity return $ AST.CSISm $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps) +mkConcSm sigs (UncondDef src dst) = do + let src_name = AST.NSimple (getSignalId $ signalInfo sigs src) + let src_expr = AST.PrimName src_name + let src_wform = AST.Wform [AST.WformElem src_expr Nothing] + let dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst) + let assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing) + return $ AST.CSSASm assign + mkAssocElems :: [(SignalId, SignalInfo)] -- | The signals in the current architecture -> [SignalMap] -- | The signals that are applied to function