From: Matthijs Kooijman <matthijs@stdin.nl>
Date: Wed, 31 Mar 2010 11:01:47 +0000 (+0200)
Subject: Log the time needed for compilation.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=698083a1ebd4a9a978b162398022ed0e45f15075;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Log the time needed for compilation.
---

diff --git "a/c\316\273ash/CLasH/Translator.hs" "b/c\316\273ash/CLasH/Translator.hs"
index 04b7beb..79bd8d2 100644
--- "a/c\316\273ash/CLasH/Translator.hs"
+++ "b/c\316\273ash/CLasH/Translator.hs"
@@ -12,6 +12,8 @@ import qualified Control.Monad.Trans.State as State
 import Text.PrettyPrint.HughesPJ (render)
 import Data.Accessor.Monad.Trans.State
 import qualified Data.Map as Map
+import qualified Data.Time.Clock as Clock
+import Debug.Trace
 
 -- GHC API
 import qualified CoreSyn
@@ -71,6 +73,7 @@ makeVHDL ::
   -> Finder
   -> IO ()
 makeVHDL libdir filenames finder = do
+  start <- Clock.getCurrentTime
   -- Load the modules
   (cores, env, specs) <- loadModules libdir filenames (Just finder)
   -- Translate to VHDL
@@ -80,7 +83,9 @@ makeVHDL libdir filenames finder = do
   let dir = "./vhdl/" ++ (show top_entity) ++ "/"
   prepareDir dir
   mapM_ (writeVHDL dir) vhdl
-  return ()
+  end <- Clock.getCurrentTime
+  trace ("\nTotal compilation took " ++ show (Clock.diffUTCTime end start)) $
+    return ()
 
 -- | Translate the specified entities in the given modules to VHDL.
 moduleToVHDL ::