From: Christiaan Baaij <christiaan.baaij@gmail.com>
Date: Fri, 7 Aug 2009 07:22:52 +0000 (+0200)
Subject: State newtype has been moved to CLasH.HardwareTypes
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=655444253776431f0949cafce2b991d12613fe04;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

State newtype has been moved to CLasH.HardwareTypes
---

diff --git a/Alu.hs b/Alu.hs
index b7fff90..1c60c04 100644
--- a/Alu.hs
+++ b/Alu.hs
@@ -12,8 +12,6 @@ mainIO = Sim.simulateIO exec initial_state
 
 dontcare = Low
 
-newtype State s = State s deriving (P.Show)
-
 program = [
             -- (addr, we, op)
             (High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
diff --git "a/c\316\273ash/CLasH/HardwareTypes.hs" "b/c\316\273ash/CLasH/HardwareTypes.hs"
index 9209086..682cd05 100644
--- "a/c\316\273ash/CLasH/HardwareTypes.hs"
+++ "b/c\316\273ash/CLasH/HardwareTypes.hs"
@@ -8,6 +8,7 @@ module CLasH.HardwareTypes
   , module Data.SizedWord
   , module Prelude
   , Bit(..)
+  , State(..)
   , Vector
   , hwand
   , hwor
@@ -29,6 +30,8 @@ import Data.SizedWord
 import Language.Haskell.TH.Lift
 import Data.Typeable
 
+newtype State s = State s deriving (P.Show)
+
 type Vector = TFVec.TFVec
 
 -- The plain Bit type