From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Fri, 3 Jul 2009 11:16:55 +0000 (+0200)
Subject: Put a TypeState in TransformState.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=3b0ce3044e2c62906a4b26cd7e1b004fea88c21e;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Put a TypeState in TransformState.

This will allow transforms to test if a Type is representable in VHDL.
---

diff --git a/NormalizeTools.hs b/NormalizeTools.hs
index 4eedb15..1785eed 100644
--- a/NormalizeTools.hs
+++ b/NormalizeTools.hs
@@ -234,5 +234,4 @@ substitute ((b, e):subss) expr = substitute subss' expr'
 -- Run a given TransformSession. Used mostly to setup the right calls and
 -- an initial state.
 runTransformSession :: UniqSupply.UniqSupply -> TransformSession a -> a
-runTransformSession uniqSupply session = State.evalState session initState
-                       where initState = TransformState uniqSupply Map.empty VarSet.emptyVarSet
+runTransformSession uniqSupply session = State.evalState session (emptyTransformState uniqSupply)
diff --git a/NormalizeTypes.hs b/NormalizeTypes.hs
index 5c7c24a..89ed53d 100644
--- a/NormalizeTypes.hs
+++ b/NormalizeTypes.hs
@@ -20,12 +20,16 @@ import Outputable ( Outputable, showSDoc, ppr )
 -- Local imports
 import CoreShow
 import Pretty
+import VHDLTypes -- For TypeState
 
 data TransformState = TransformState {
     tsUniqSupply_ :: UniqSupply.UniqSupply
   , tsBindings_ :: Map.Map CoreBndr CoreExpr
   , tsNormalized_ :: VarSet.VarSet -- ^ The binders that have been normalized
+  , tsType_ :: TypeState
 }
+-- Create an (almost) empty TransformState, containing just a UniqSupply.
+emptyTransformState uniqSupply = TransformState uniqSupply Map.empty VarSet.emptyVarSet emptyTypeState
 
 $( Data.Accessor.Template.deriveAccessors ''TransformState )