From: Matthijs Kooijman <matthijs@stdin.nl>
Date: Tue, 8 Dec 2009 17:10:57 +0000 (+0100)
Subject: Fix references to the inverter examples.
X-Git-Tag: final-thesis~27
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=391f3ab5a3e21567b1b1b62b1c7ed47fcdb40886;p=matthijs%2Fmaster-project%2Freport.git

Fix references to the inverter examples.
---

diff --git a/Chapters/HardwareDescription.tex b/Chapters/HardwareDescription.tex
index cac03ed..3179cfe 100644
--- a/Chapters/HardwareDescription.tex
+++ b/Chapters/HardwareDescription.tex
@@ -193,13 +193,16 @@ and3 a b c = and (and a b) c
     simply be translated to a conditional assignment, where the conditions use
     equality comparisons against the constructors in the \hs{case} expressions.
 
-    In \in{example}[ex:CaseInv] a simple \hs{case} expression is shown,
-    scrutinizing a boolean value. The corresponding architecture has a
-    comparator to determine which of the constructors is on the \hs{in}
-    input. There is a multiplexer to select the output signal. The two options
-    for the output signals are just constants, but these could have been more
-    complex expressions (in which case also both of them would be working in
-    parallel, regardless of which output would be chosen eventually).
+    In \in{example}[ex:Inv] two versions of an inverter are shown. The first
+    uses a simple \hs{case} expression, scrutinizing a boolean value.  The
+    corresponding architecture has a comparator to determine which of the
+    constructors is on the \hs{in} input. There is a multiplexer to select the
+    output signal (which is just a conditional assignment in the generated
+    \VHDL). The two options for the output signals are just constants,
+    but these could have been more complex expressions (in which case also
+    both of them would be working in parallel, regardless of which output
+    would be chosen eventually). The \VHDL\ generated for (both versions of)
+    this inverter is shown in \in{example}[ex:InvVHDL].
 
     If we would translate a Boolean to a bit value, we could of course remove
     the comparator and directly feed 'in' into the multiplexer (or even use an
@@ -233,8 +236,9 @@ and3 a b c = and (and a b) c
     specifies a pattern. When the arguments match the pattern, the
     corresponding clause will be used.
 
-    The architecture described by \in{example}[ex:PatternInv] is of course the
-    same one as the one in \in{example}[ex:CaseInv]. The general interpretation
+    \in{Example}[ex:Inv] also shows an inverter that uses pattern matching.
+    The architecture it describes is of course the
+    same one as the description with a case expression. The general interpretation
     of pattern matching is also similar to that of \hs{case} expressions: generate
     hardware for each of the clauses (like each of the clauses of a \hs{case}
     expression) and connect them to the function output through (a number of
@@ -335,7 +339,7 @@ and3 a b c = and (and a b) c
 %          {\boxedgraphic{Inv}}{The architecture described by the Haskell description.}
 %        \stopcombination
 %    }
-    \placeexample[][ex:InvVHDL]{\VHDL\ generated for \hs{inv} from \in{example}[ex:Inv]}
+    \placeexample[][ex:InvVHDL]{\VHDL\ generated for (both versions of) \hs{inv} from \in{example}[ex:Inv]}
         {\typebuffervhdl{InvVHDL}}
 
   \section{Types}