From: christiaanb Date: Wed, 31 Mar 2010 13:07:28 +0000 (+0200) Subject: Update reducer to latest design (that runs at 159 MHz) X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=344076ec6d72b65849e05c746e0429c927c7d43d;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Update reducer to latest design (that runs at 159 MHz) --- diff --git a/reducer.hs b/reducer.hs index 410b881..925e7f6 100644 --- a/reducer.hs +++ b/reducer.hs @@ -1,56 +1,44 @@ -{-# LANGUAGE TypeOperators, TemplateHaskell, FlexibleContexts, TypeFamilies, ScopedTypeVariables, RecordWildCards #-} -module Main where +{-# LANGUAGE TypeOperators, TemplateHaskell, FlexibleContexts, TypeFamilies, + ScopedTypeVariables, RecordWildCards #-} +module Reducer where -import System.Random -import System.IO.Unsafe (unsafePerformIO,unsafeInterleaveIO) import qualified Prelude as P -import CLasH.HardwareTypes +import CLasH.HardwareTypes hiding ((>>)) import CLasH.Translator.Annotations +type Signed = SizedInt +type Unsigned = SizedWord +type Index = RangedWord + -- ======================================= -- = System size configuration variables = -- ======================================= - -type DataSize = D8 -type IndexSize = D8 +type DataSize = D64 +type IndexSize = D16 type DiscrSize = D7 -type DiscrRange = D127 -type AdderDepth = D14 +type AdderDepth = D12 + +-- Derived configuration variables +type DiscrRange = (Pow2 DiscrSize) :-: D1 +type AdderDepthPL = AdderDepth :+: D3 -- ================= -- = Type Aliasses = -- ================= - -type Shift = RangedWord D2 -type DataInt = SizedWord DataSize -type ArrayIndex = SizedWord IndexSize -type Discr = RangedWord DiscrRange - -type OutputSignal = ( ( DataInt - , ArrayIndex - ) - , Bool - ) - -data CellType = Valid | NotValid - deriving (Eq) - -type Cell = ( CellType - , ( DataInt - , Discr - ) - ) - -notValid :: Cell -notValid = (NotValid,(0::DataInt,0::Discr)) - --- ================================ --- = Cell type accessor functions = --- ================================ +type Shift = Index D2 +type DataInt = Signed DataSize +type ArrayIndex = Unsigned IndexSize +type Discr = Index DiscrRange +type OutputSignal = ((DataInt, ArrayIndex), Bool) + +-- ================================= +-- = Cell Definition and Accessors = +-- ================================= +type CellType = Bool +type Cell = (CellType, (DataInt, Discr)) valid :: Cell -> Bool -valid (Valid, _) = True -valid _ = False +valid (x, _) = x value :: Cell -> DataInt value (_, (v, _)) = v @@ -58,219 +46,314 @@ value (_, (v, _)) = v discr :: Cell -> Discr discr (_, (_, d)) = d +notValid :: Cell +notValid = (False, (0, 0)) + +-- ==================== +-- = Helper functions = +-- ==================== +v << e = shiftr v e +e >> v = shiftl v e + -- ======================= -- = Reducer State types = -- ======================= - -data DiscrRecord = DiscrR { prev_index :: ArrayIndex - , cur_discr :: SizedWord DiscrSize - } - -type DiscrState = State DiscrRecord - -data CircRecord = Circ { mem :: Vector (AdderDepth :+: D1) (DataInt, Discr) - , rdptr :: RangedWord AdderDepth - , wrptr :: RangedWord AdderDepth - , count :: RangedWord (AdderDepth :+: D1) - } - -type CircState = State CircRecord - -type FpAdderState = State (Vector AdderDepth Cell) - -data OutputRecord = Outp { res_mem :: RAM DiscrRange Cell - , lut :: MemState DiscrRange ArrayIndex - } - -type OutputState = State OutputRecord - -data OutputRecordO = OutpO { valid_mem :: RAM DiscrRange CellType - , mem1 :: MemState DiscrRange DataInt - , mem2 :: MemState DiscrRange DataInt - , lutm :: MemState DiscrRange ArrayIndex - } +data DiscrRecord = + DiscrR { prev_index :: ArrayIndex + , cur_discr :: SizedWord DiscrSize + } +type DiscrState = State DiscrRecord -type OutputStateO = State OutputRecordO - -data ReducerRecord = Reducer { discrState :: DiscrState - , inputState :: CircState - , pipeState :: FpAdderState - , resultState :: OutputStateO - } - +type RippleState = + State (Vector (AdderDepthPL :+: D1) (CellType, Discr)) + +data BlockRecord = + Block { ptrs :: (SizedWord D4, SizedWord D4, SizedWord D4) + , buf1 :: MemState AdderDepthPL DataInt + , buf2 :: MemState AdderDepthPL DataInt + } +type BlockState = State BlockRecord + +type FpAdderState = + State ( ( (DataInt, DataInt, DataInt, DataInt) -- Buffer input and double buffer output of the FPAdder + , Vector AdderDepthPL (CellType, Discr) -- Validbits & discriminators of values in the FP pipeline + ) + , FpPlaceholder + ) + +type FpPlaceholder = + State (Vector AdderDepth DataInt) + +data OutputRecord = + Outp { valid_mem :: RAM DiscrRange CellType + , mem1 :: MemState DiscrRange DataInt + , mem2 :: MemState DiscrRange DataInt + , lutm :: MemState DiscrRange ArrayIndex + } +type OutputState = State OutputRecord + +data ReducerRecord = + Reducer { discrState :: DiscrState + , rippleState :: RippleState + , blockState :: BlockState + , pipeState :: FpAdderState + , resultState :: OutputState + , pipeline :: ( Vector AdderDepth (Discr, ArrayIndex, Bool) -- Buffer link between discriminator and Result buffer + , CellType -- Buffer Valid bit of the resultbuffer at T+1 + , Vector D2 (DataInt, ArrayIndex) -- Buffer Input (to encourage retiming) + , Vector D2 OutputSignal -- Buffer Output (to encourage retiming) + ) + } type ReducerState = State ReducerRecord -- =========================================================== -- = Discrimintor: Hands out new discriminator to the system = -- =========================================================== {-# ANN discriminator (InitState 'initDiscrState) #-} -discriminator :: DiscrState -> (DataInt, ArrayIndex) -> (DiscrState, (DataInt, Discr), Bool) -discriminator (State (DiscrR {..})) (data_in, index) = ( State ( DiscrR { prev_index = index - , cur_discr = cur_discr' - }) - , (data_in, discr) - , new_discr - ) +discriminator :: + DiscrState -> + ArrayIndex -> + (DiscrState, Discr, Bool) +discriminator (State (DiscrR {..})) index = ( State DiscrR { prev_index = index + , cur_discr = cur_discr' + } + , discr + , new_discr + ) where - new_discr = index /= prev_index - cur_discr' | new_discr = cur_discr + 1 - | otherwise = cur_discr - discr = fromSizedWord cur_discr' + new_discr = index /= prev_index + cur_discr' | new_discr = cur_discr + 1 + | otherwise = cur_discr + discr = fromSizedWord cur_discr' -- ====================================================== -- = Input Buffer: Buffers incomming inputs when needed = -- ====================================================== -{-# ANN circBuffer (InitState 'initCircState) #-} -circBuffer :: CircState -> - ((DataInt, Discr), Shift) -> - (CircState, Cell, Cell) -circBuffer (State (Circ {..})) (inp,shift) = ( State ( Circ { mem = mem' - , rdptr = rdptr' - , wrptr = wrptr' - , count = count' - }) - , out1, out2 - ) +{-# ANN rippleBuffer (InitState 'initRippleState) #-} +rippleBuffer :: + RippleState -> + (Discr, Shift) -> + (RippleState, (CellType, Discr), (CellType, Discr)) +rippleBuffer (State buf) (inp, shift) = (State buf', out1, out2) where - (n :: RangedWord AdderDepth) = fromInteger (fromIntegerT (undefined :: AdderDepth)) - (rdptr',count') | shift == 0 = (rdptr , count + 1) - | shift == 1 = if rdptr == 0 then (n , count ) else - (rdptr - 1, count ) - | otherwise = if rdptr == 1 then (n , count - 1) else - if rdptr == 0 then (n - 1 , count - 1) else - (rdptr - 2, count - 1) - rdptr2 | rdptr == 0 = n - | otherwise = rdptr - 1 - wrptr' = if wrptr == 0 then n else wrptr - 1 - mem' = replace mem wrptr inp - out1 | count == 0 = notValid - | otherwise = (Valid,mem!rdptr) - out2 | count <= 1 = notValid - | otherwise = (Valid,mem!rdptr2) + -- Write value + next_valids = (map fst buf) << True + buf'' = zipWith selects buf next_valids + selects cell next_valid = if (not (fst cell)) && next_valid then + (True, inp) + else + cell + -- Shift values + buf' | shift == 2 = (False, 0) >> ((False, 0) >> buf'') + | shift == 1 = (False, 0) >> buf'' + | otherwise = buf'' + -- Read values + out1 = last buf + out2 = last (init buf) + +{-# ANN blockBuffer (InitState 'initBlockState) #-} +blockBuffer :: + BlockState -> + (DataInt, Shift) -> + (BlockState, DataInt, DataInt) +blockBuffer (State (Block {..})) (inp, shift) = ( State Block { ptrs = ptrs' + , buf1 = buf1' + , buf2 = buf2' + } + , out1, out2) + where + -- Do some state (un)packing + (rd_ptr1, rd_ptr2, wr_ptr) = ptrs + ptrs' = (rd_ptr1', rd_ptr2', wr_ptr') + -- Update pointers + count = fromRangedWord shift + (rd_ptr1', rd_ptr2') = (rd_ptr1 + count, rd_ptr2 + count) + wr_ptr' = wr_ptr + 1 + -- Write & Read from RAMs + (buf1', out1) = blockRAM buf1 inp (fromSizedWord rd_ptr1) (fromSizedWord wr_ptr) True + (buf2', out2) = blockRAM buf2 inp (fromSizedWord rd_ptr2) (fromSizedWord wr_ptr) True -- ============================================ -- = Simulated pipelined floating point adder = -- ============================================ {-# ANN fpAdder (InitState 'initPipeState) #-} -fpAdder :: FpAdderState -> (Cell, Cell) -> (FpAdderState, Cell) -fpAdder (State pipe) (arg1, arg2) = (State pipe', pipe_out) +fpAdder :: + FpAdderState -> + (Cell, Cell) -> + (FpAdderState, (Cell, Cell)) +fpAdder (State ((buffer, pipe), adderState)) (arg1, arg2) = (State ((buffer', pipe'), adderState'), (pipeT_1, pipeT)) where - new_head | valid arg1 = (Valid, ((value arg1 + value arg2), discr arg1)) - | otherwise = notValid - - pipe' = new_head +> init pipe - pipe_out = last pipe - --- ============================================================== --- = Partial Results buffers, purges completely reduced results = --- ============================================================== -resBuff :: OutputState -> ( Cell, Cell, ArrayIndex, (Discr, Bool)) -> (OutputState, Cell, OutputSignal) -resBuff (State (Outp {..})) (pipe_out, new_cell, index, (discrN, new_discr)) = ( State ( Outp { res_mem = res_mem'' - , lut = lut' - }) - , res_mem_out, output) + -- Do some state (un)packing + (a1,a2,dataT_1,dataT) = buffer + buffer' = (value arg1, value arg2, adderOut, dataT_1) + -- placeholder adder + (adderState', adderOut) = fpPlaceholder adderState (a1, a2) + -- Save corresponding indexes and valid bits + pipe' = (valid arg1, discr arg1) >> pipe + -- Produce output for time T and T+1 + pipeEndT = last pipe + pipeEndT_1 = last (init pipe) + pipeT = (fst pipeEndT, (dataT, snd pipeEndT)) + pipeT_1 = (fst pipeEndT_1,(dataT_1,snd pipeEndT_1)) + +{-# ANN fpPlaceholder (InitState 'initAdderState) #-} +fpPlaceholder :: FpPlaceholder -> (DataInt, DataInt) -> (FpPlaceholder, DataInt) +fpPlaceholder (State pipe) (arg1, arg2) = (State pipe', pipe_out) where - -- Purge completely reduced results from the system - clean_mem | new_discr = replace res_mem discrN notValid - | otherwise = res_mem - -- If a partial is fed back to the pipeline, make its location invalid - res_mem' | valid pipe_out = replace clean_mem (discr pipe_out) notValid - | otherwise = clean_mem - -- Write a new partial to memory if it is valid - res_mem'' | valid new_cell = replace res_mem' (discr new_cell) new_cell - | otherwise = res_mem' - -- Output a partial if it is needed, otherwise output invalid - res_mem_out | valid pipe_out = res_mem ! (discr pipe_out) - | otherwise = notValid - -- Lut maps discriminators to array index - (lut', lut_out) = blockRAM lut index discrN discrN new_discr - -- Output value to the system once a discriminator is reused - output' = res_mem ! discrN - output = ( (value output', lut_out) - , new_discr && valid output' - ) + pipe' = (arg1 + arg2) +> init pipe + pipe_out = last pipe -- =================================================== -- = Optimized Partial Result Buffer, uses BlockRAMs = -- =================================================== -{-# ANN resBuffO (InitState 'initResultState) #-} -resBuffO :: OutputStateO -> ( Cell, Cell, ArrayIndex, (Discr, Bool)) -> (OutputStateO, Cell, OutputSignal) -resBuffO (State (OutpO {..})) (pipe_out, new_cell, index, (discrN, new_discr)) = ( State ( OutpO { valid_mem = valid_mem' - , mem1 = mem1' - , mem2 = mem2' - , lutm = lutm' - }) - , res_mem_out, output) +{-# ANN resBuff (InitState 'initResultState) #-} +resBuff :: + OutputState -> + ( Cell, Cell, Bool, (Discr, ArrayIndex, Bool)) -> + (OutputState, Cell, OutputSignal) +resBuff (State (Outp {..})) (pipeT, pipeT_1, new_cell, (discrN, index, new_discr)) = ( State Outp { valid_mem = valid_mem' + , mem1 = mem1' + , mem2 = mem2' + , lutm = lutm' + } + , res_mem_out, output) where - addr = discr pipe_out + addrT = discr pipeT + addrT_1 = discr pipeT_1 -- Purge completely reduced results from the system - clean_mem | new_discr = replace valid_mem discrN NotValid + clean_mem | new_discr = replace valid_mem discrN False | otherwise = valid_mem -- If a partial is fed back to the pipeline, make its location invalid - valid_mem' | valid new_cell = replace clean_mem addr Valid - | otherwise = replace clean_mem addr NotValid + valid_mem' | new_cell = replace clean_mem addrT True + | otherwise = replace clean_mem addrT False -- Two parrallel memories with the same write addr, but diff rdaddr for partial res and other for complete res - (mem1', partial) = blockRAM mem1 (value new_cell) addr addr (valid new_cell) - (mem2', complete) = blockRAM mem2 (value new_cell) discrN addr (valid new_cell) + (mem1', partial) = blockRAM mem1 (value pipeT) addrT addrT new_cell + (mem2', complete) = blockRAM mem2 (value pipeT) discrN addrT new_cell -- Lut maps discriminators to array index (lutm', lut_out) = blockRAM lutm index discrN discrN new_discr - res_mem_out = (valid_mem!addr, (partial,addr)) + res_mem_out = (valid_mem!addrT_1, (partial,addrT)) -- Output value to the system once a discriminator is reused - output = ((complete,lut_out), new_discr && (valid_mem!discrN) == Valid) + output = ((complete,lut_out), new_discr && (valid_mem!discrN)) -- ================================================================ -- = Controller guides correct inputs to the floating point adder = -- ================================================================ -controller :: (Cell, Cell, Cell, Cell) -> (Cell, Cell, Shift, Cell) -controller (inp1, inp2, pipe_out, from_res_mem) = (arg1, arg2, shift, to_res_mem) +controller :: + (Cell, Cell, Cell, Cell) -> + (Cell, Cell, Shift, Bool) +controller (inp1, inp2, pipeT, from_res_mem) = (arg1, arg2, shift, to_res_mem) where (arg1, arg2, shift, to_res_mem) - | valid pipe_out && valid from_res_mem = (pipe_out, from_res_mem , 0, notValid) - | valid pipe_out && valid inp1 && discr pipe_out == discr inp1 = (pipe_out, inp1 , 1, notValid) - | valid inp1 && valid inp2 && discr inp1 == discr inp2 = (inp1 , inp2 , 2, pipe_out) - | valid inp1 = (inp1 , (Valid, (0, discr inp1)), 1, pipe_out) - | otherwise = (notValid, notValid , 0, pipe_out) + | valid pipeT && valid from_res_mem = (pipeT , from_res_mem , 0, False) + | valid pipeT && valid inp1 && discr pipeT == discr inp1 = (pipeT , inp1 , 1, False) + | valid inp1 && valid inp2 && discr inp1 == discr inp2 = (inp1 , inp2 , 2, valid pipeT) + | valid inp1 = (inp1 , (True, (0, discr inp1)) , 1, valid pipeT) + | otherwise = (notValid, notValid , 0, valid pipeT) -- ============================================= -- = Reducer: Wrap up all the above components = -- ============================================= {-# ANN reducer TopEntity #-} -reducer :: ReducerState -> (DataInt, ArrayIndex) -> (ReducerState, OutputSignal) -reducer (State (Reducer {..})) (data_in, index) = (reducerState',output) +{-# ANN reducer (InitState 'initReducerState) #-} +reducer :: + ReducerState -> + (DataInt, ArrayIndex) -> + (ReducerState, OutputSignal) +reducer (State (Reducer {..})) (data_in, index) = ( State Reducer { discrState = discrState' + , rippleState = rippleState' + , blockState = blockState' + , pipeState = pipeState' + , resultState = resultState' + , pipeline = pipeline' + } + , last outPipe) where - (discrState' , inpcell@(_,discrN), new_discr) = discriminator discrState (data_in,index) - (inputState' , inp1 , inp2) = circBuffer inputState (inpcell, shift) - (pipeState' , pipe_out) = fpAdder pipeState (arg1, arg2) - (resultState', from_res_mem, output) = resBuffO resultState (pipe_out, to_res_mem, index, (discrN, new_discr)) - (arg1,arg2,shift,to_res_mem) = controller (inp1, inp2, pipe_out, from_res_mem) - reducerState' = State ( Reducer { discrState = discrState' - , inputState = inputState' - , pipeState = pipeState' - , resultState = resultState' - }) - --- ------------------------------------------------------- --- -- Test Functions --- ------------------------------------------------------- --- --- "Default" Run function + -- Discriminator + (discrState' , discrN, new_discr) = discriminator discrState (snd (last inPipe)) + -- InputBuffer + (rippleState' , (inp1V, inp1I), (inp2V, inp2I)) = rippleBuffer rippleState (discrN, shift) + (blockState', inp1D, inp2D) = blockBuffer blockState ((fst (last inPipe)), shift) + (inp1,inp2) = ((inp1V,(inp1D,inp1I)),(inp2V,(inp2D,inp2I))) + -- FP Adder + (pipeState' , (pipeT_1, pipeT)) = fpAdder pipeState (arg1, arg2) + -- Result Buffer + (resultState', from_res_mem, output') = resBuff resultState (pipeT, pipeT_1, to_res_mem, last discrO) + -- Controller + (arg1,arg2,shift,to_res_mem) = controller (inp1, inp2, pipeT, (valT, snd from_res_mem)) + -- Optimizations/Pipelining + valT_1 | discr pipeT == discr pipeT_1 = not (valid from_res_mem) + | otherwise = valid from_res_mem + (discrO, valT, inPipe , outPipe) = pipeline + pipeline' = ( (discrN, index, new_discr) >> discrO + , valT_1 + , (data_in, index) >> inPipe + , output' >> outPipe + ) + + +-- ======================== +-- = Initial State values = +-- ======================== +initDiscrState :: DiscrRecord +initDiscrState = DiscrR { prev_index = 255 + , cur_discr = 127 + } + +initRippleState :: Vector (AdderDepthPL :+: D1) (CellType, Discr) +initRippleState = copy (False, 0) + +initBlockState :: (SizedWord D4, SizedWord D4, SizedWord D4) +initBlockState = (0,1,0) + +initPipeState :: + ((DataInt,DataInt,DataInt,DataInt) + , Vector AdderDepthPL (CellType, Discr) + ) +initPipeState = ((0,0,0,0),copy (False, 0)) + +initAdderState :: Vector AdderDepth DataInt +initAdderState = copy 0 + +initResultState :: RAM DiscrRange CellType +initResultState = copy False + +initReducerState :: + ( Vector AdderDepth (Discr, ArrayIndex, Bool) + , CellType + , Vector D2 (DataInt, ArrayIndex) + , Vector D2 OutputSignal + ) +initReducerState = (copy (0, 0, False), False, copy (0,0), copy ((0,0), False)) + +initstate :: ReducerState +initstate = State ( Reducer { discrState = State initDiscrState + , rippleState = State initRippleState + , blockState = State Block { ptrs = initBlockState + , buf1 = State (copy 0) + , buf2 = State (copy 0) + } + , pipeState = State (initPipeState, State initAdderState) + , resultState = State Outp { valid_mem = initResultState + , mem1 = State (copy 0) + , mem2 = State (copy 0) + , lutm = State (copy 0) + } + , pipeline = initReducerState + }) + +-- ================== +-- = Test Functions = +-- ================== run func state [] = [] run func state (i:input) = o:out where (state', o) = func state i out = run func state' input -runReducerIO :: IO () -runReducerIO = do - let input = siminput - let istate = initstate - let output = run reducer istate input - mapM_ (\x -> putStr $ ((show x) P.++ "\n")) output - return () - runReducer = ( reduceroutput , validoutput , equal + , allEqual ) where -- input = randominput 900 7 @@ -283,55 +366,7 @@ runReducer = ( reduceroutput (filter (\x -> (snd x) == i) input)) | i <- [0..30]] equal = [validoutput!!i == toInteger (fst (reduceroutput!!i)) | i <- [0..30]] - --- Generate infinite list of numbers between 1 and 'x' -randX :: Integer -> [Integer] -randX x = randomRs (1,x) (unsafePerformIO newStdGen) - --- Generate random lists of indexes -randindex 15 i = randindex 1 i -randindex m i = (P.take n (repeat i)) P.++ (randindex (m+1) (i+1)) - where - [n] = P.take 1 rnd - rnd = randomRs (1,m) (unsafePerformIO newStdGen) - --- Combine indexes and values to generate random input for the reducer -randominput n x = P.zip data_in index_in - where - data_in = P.map (fromInteger :: Integer -> DataInt) (P.take n (randX x)) - index_in = P.map (fromInteger :: Integer -> ArrayIndex) - (P.take n (randindex 7 0)) -main = runReducerIO - -initDiscrState :: DiscrRecord -initDiscrState = DiscrR { prev_index = (255 :: ArrayIndex) - , cur_discr = (127 :: SizedWord DiscrSize) - } - -initCircState :: CircRecord -initCircState = Circ { mem = copy (0::DataInt,0::Discr) - , rdptr = (14 :: RangedWord AdderDepth) - , wrptr = (14 :: RangedWord AdderDepth) - , count = (0 :: RangedWord (AdderDepth :+: D1)) - } - -initPipeState :: Vector AdderDepth Cell -initPipeState = copy notValid - -initResultState :: RAM DiscrRange CellType -initResultState = copy NotValid - -initstate :: ReducerState -initstate = State ( Reducer { discrState = State initDiscrState - , inputState = State initCircState - , pipeState = State initPipeState - , resultState = State OutpO { valid_mem = initResultState - , mem1 = State (copy (0::DataInt)) - , mem2 = State (copy (0::DataInt)) - , lutm = State (copy (0::ArrayIndex)) - } - }) + allEqual = foldl1 (&&) equal -{-# ANN siminput TestInput #-} siminput :: [(DataInt, ArrayIndex)] siminput = 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