From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Fri, 13 Feb 2009 11:39:29 +0000 (+0100)
Subject: Add the VHDLTypes module
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=30a05fb3678f430135654b3f5d6612b409b7cd39;hp=6fabab8e6243062ab74860ca90bb4b08f564ceff;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Add the VHDLTypes module

This file should have been added a few commits back already...
---

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
new file mode 100644
index 0000000..34a2b50
--- /dev/null
+++ b/VHDLTypes.hs
@@ -0,0 +1,19 @@
+--
+-- Some types used by the VHDL module.
+--
+module VHDLTypes where
+
+import qualified ForSyDe.Backend.VHDL.AST as AST
+
+import FlattenTypes
+
+type VHDLSignalMap = SignalMap AST.VHDLId
+
+-- A description of a VHDL entity. Contains both the entity itself as well as
+-- info on how to map a haskell value (argument / result) on to the entity's
+-- ports.
+data Entity = Entity {
+  ent_args   :: [VHDLSignalMap],      -- A mapping of each function argument to port names
+  ent_res    :: VHDLSignalMap,        -- A mapping of the function result to port names
+  ent_decl   :: Maybe AST.EntityDec   -- The actual entity declaration. Can be empty for builtin functions.
+}