From: Christiaan Baaij Date: Mon, 22 Feb 2010 16:07:47 +0000 (+0100) Subject: Add figure of stateful Multiply-Accumulate X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=22f8cee93ef48cda79d851f949b6f978a86d7fc3;p=matthijs%2Fmaster-project%2Fdsd-paper.git Add figure of stateful Multiply-Accumulate --- diff --git "a/c\316\273ash.lhs" "b/c\316\273ash.lhs" index 07a49f4..dd08c38 100644 --- "a/c\316\273ash.lhs" +++ "b/c\316\273ash.lhs" @@ -751,7 +751,7 @@ by an optimizing \VHDL\ synthesis tool. completely new type, for which we provide the \VHDL\ translation below. Type synonyms and renamings only define new names for existing types, where synonyms are completely interchangeable and - renamings need explicit conversion. Therefore, these do not need + renamings need explicit conversiona. Therefore, these do not need any particular \VHDL\ translation, a synonym or renamed type will just use the same representation as the original type. The distinction between a renaming and a synonym does no longer matter @@ -990,12 +990,16 @@ by an optimizing \VHDL\ synthesis tool. A simple example is the description of an accumulator circuit: \begin{code} - acc :: Word -> State Word -> (State Word, Word) - acc inp (State s) = (State s', outp) + macS a b (State c) = (State c', outp) where - outp = s + inp - s' = outp + outp = mac a b c + c' = outp \end{code} + \begin{figure} + \centerline{\includegraphics{mac-state}} + \caption{Stateful Multiply-Accumulate} + \label{img:mac-state} + \end{figure} This approach makes the state of a function very explicit: which variables are part of the state is completely determined by the type signature. This approach to state is well suited to be used in combination with the diff --git a/mac-state.svg b/mac-state.svg new file mode 100644 index 0000000..8f40046 --- /dev/null +++ b/mac-state.svg @@ -0,0 +1,277 @@ + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +