From: Matthijs Kooijman Date: Wed, 24 Jun 2009 10:03:38 +0000 (+0200) Subject: Remove the globalNameTable from the VHDLState. X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=12fc969daa4ca2dfc69ab68f27684dd6b01622f3;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git Remove the globalNameTable from the VHDLState. The globalNameTable is never modified, so it can just be referenced directly. Additionally, having it in the VHDLSession prevents us from putting the Builder type in the VHDLSession Monad. --- diff --git a/VHDL.hs b/VHDL.hs index 7073dbc..636634e 100644 --- a/VHDL.hs +++ b/VHDL.hs @@ -47,7 +47,7 @@ createDesignFiles binds = map (Arrow.second $ AST.DesignFile full_context) units where - init_session = VHDLState Map.empty Map.empty Map.empty Map.empty globalNameTable + init_session = VHDLState Map.empty Map.empty Map.empty Map.empty (units, final_session) = State.runState (createLibraryUnits binds) init_session tyfun_decls = Map.elems (final_session ^.vsTypeFuns) @@ -294,9 +294,8 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do IdInfo.VanillaGlobal -> do -- It's a global value imported from elsewhere. These can be builtin -- functions. - funSignatures <- getA vsNameTable signatures <- getA vsSignatures - case (Map.lookup (varToString f) funSignatures) of + case (Map.lookup (varToString f) globalNameTable) of Just (arg_count, builder) -> if length valargs == arg_count then case builder of diff --git a/VHDLTypes.hs b/VHDLTypes.hs index fe739da..59da9c1 100644 --- a/VHDLTypes.hs +++ b/VHDLTypes.hs @@ -54,11 +54,6 @@ type TypeFunMap = Map.Map OrdType [AST.SubProgBody] -- A map of a Haskell function to a hardware signature type SignatureMap = Map.Map CoreSyn.CoreBndr Entity -type Builder = Either ([AST.Expr] -> AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm) - --- A map of a builtin function to VHDL function builder -type NameTable = Map.Map String (Int, Builder ) - data VHDLState = VHDLState { -- | A map of Core type -> VHDL Type vsTypes_ :: TypeMap, @@ -68,9 +63,7 @@ data VHDLState = VHDLState { vsTypeFuns_ :: TypeFunMap, -- | A map of HsFunction -> hardware signature (entity name, port names, -- etc.) - vsSignatures_ :: SignatureMap, - -- | A map of Vector HsFunctions -> VHDL function call - vsNameTable_ :: NameTable + vsSignatures_ :: SignatureMap } -- Derive accessors @@ -82,4 +75,9 @@ type VHDLSession = State.State VHDLState -- | A substate containing just the types type TypeState = State.State TypeMap +type Builder = Either ([AST.Expr] -> AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm) + +-- A map of a builtin function to VHDL function builder +type NameTable = Map.Map String (Int, Builder ) + -- vim: set ts=8 sw=2 sts=2 expandtab: