From: Matthijs Kooijman <matthijs@stdin.nl>
Date: Tue, 1 Sep 2009 14:39:20 +0000 (+0200)
Subject: Merge branch 'master' of git://github.com/christiaanb/clash into cλash
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=0943241695de7bd2845afa1329b973e0f173a3a2;hp=ac1b16498d945e9a9ece8b061ddd2cd00d1172b5;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Merge branch 'master' of git://github.com/christiaanb/clash into cλash

* 'master' of git://github.com/christiaanb/clash:
  Use boolean as write enable signal
---

diff --git "a/c\316\273ash/CLasH/HardwareTypes.hs" "b/c\316\273ash/CLasH/HardwareTypes.hs"
index cff5c88..e6e84fd 100644
--- "a/c\316\273ash/CLasH/HardwareTypes.hs"
+++ "b/c\316\273ash/CLasH/HardwareTypes.hs"
@@ -84,13 +84,14 @@ blockRAM ::
   a ->
   RangedWord s ->
   RangedWord s ->
-  Bit -> 
+  Bool -> 
   ((MemState s a), a )
 blockRAM (State mem) data_in rdaddr wraddr wrenable = 
   ((State mem'), data_out)
   where
     data_out  = mem!rdaddr
     -- Only write data_in to memory if write is enabled
-    mem' = case wrenable of
-      Low   ->  mem
-      High  ->  replace mem wraddr data_in
+    mem' =  if wrenable then
+              replace mem wraddr data_in
+            else
+              mem
diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs"
index 9e2d0a5..048a711 100644
--- "a/c\316\273ash/CLasH/VHDL/Generate.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Generate.hs"
@@ -881,7 +881,7 @@ genBlockRAM' (Left res) f args@[data_in,rdaddr,wraddr,wrenable] = do
         wform       = AST.Wform [AST.WformElem data_in Nothing]
         ramassign      = AST.SigAssign ramloc wform
         rising_edge_clk = genExprFCall rising_edge (AST.PrimName $ AST.NSimple clockId)
-        statement   = AST.IfSm (AST.And rising_edge_clk (wrenable AST.:=: AST.PrimLit "'1'")) [ramassign] [] Nothing
+        statement   = AST.IfSm (AST.And rising_edge_clk wrenable) [ramassign] [] Nothing
 
 -----------------------------------------------------------------------------
 -- Function to generate VHDL for applications