From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Tue, 23 Jun 2009 10:11:10 +0000 (+0200)
Subject: Prepend "comp_ins_" to component instantiation labels.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=050d5b03fb51d44baa1bfc4f4a4b9e4b972638d7;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Prepend "comp_ins_" to component instantiation labels.

This should ensure that these labels are fairly unique (no guarantees yet,
though).
---

diff --git a/VHDL.hs b/VHDL.hs
index 3eddd8b..00b5dda 100644
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -310,7 +310,7 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do
           (error $ "Using function '" ++ (bndrToString f) ++ "' without signature? This should not happen!") 
           (Map.lookup f signatures)
         entity_id = ent_id signature
-        label = bndrToString bndr
+        label = "comp_ins_" ++ bndrToString bndr
         -- Add a clk port if we have state
         --clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
         --portmaps = mkAssocElems sigs args res signature ++ (if hasState hsfunc then [clk_port] else [])