From: Matthijs Kooijman <m.kooijman@student.utwente.nl>
Date: Wed, 18 Feb 2009 19:27:20 +0000 (+0100)
Subject: Add a simple four-bit shift register model.
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;h=0082f01a853476cdcec0e73bacf8c0d4508dbec0;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Add a simple four-bit shift register model.

This model is already translatable to VHDL.
---

diff --git a/Adders.hs b/Adders.hs
index ce26166..ac93a33 100644
--- a/Adders.hs
+++ b/Adders.hs
@@ -39,6 +39,14 @@ dff d s = (s', q)
     q = s
     s' = d
 
+type ShifterState = (Bit, Bit, Bit, Bit)
+shifter :: Bit -> ShifterState -> (ShifterState, Bit)
+shifter a s =
+  (s', o)
+  where
+    s' = (a, b, c, d)
+    (b, c, d, o) = s
+
 -- Combinatoric stateless no-carry adder
 -- A -> B -> S
 no_carry_adder :: (Bit, Bit) -> Bit
diff --git a/Translator.hs b/Translator.hs
index c16406b..cf2fb96 100644
--- a/Translator.hs
+++ b/Translator.hs
@@ -45,7 +45,7 @@ main = do
   -- Load the module
   core <- loadModule "Adders.hs"
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["dff"]
+  vhdl <- moduleToVHDL core ["shifter"]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"