From: Matthijs Kooijman <matthijs@stdin.nl>
Date: Tue, 1 Sep 2009 14:39:20 +0000 (+0200)
Subject: Merge branch 'master' of git://github.com/christiaanb/clash into cλash
X-Git-Url: https://git.stderr.nl/gitweb?a=commitdiff_plain;ds=sidebyside;h=0943241695de7bd2845afa1329b973e0f173a3a2;hp=-c;p=matthijs%2Fmaster-project%2Fc%CE%BBash.git

Merge branch 'master' of git://github.com/christiaanb/clash into cλash

* 'master' of git://github.com/christiaanb/clash:
  Use boolean as write enable signal
---

0943241695de7bd2845afa1329b973e0f173a3a2
diff --combined "c\316\273ash/CLasH/VHDL/Generate.hs"
index 9e2d0a5,ecaad62..048a711
--- "a/c\316\273ash/CLasH/VHDL/Generate.hs"
+++ "b/c\316\273ash/CLasH/VHDL/Generate.hs"
@@@ -207,7 -207,7 +207,7 @@@ mkConcSm (bndr, app@(CoreSyn.App _ _))
    let valargs = get_val_args (Var.varType f) args
    genApplication (Left bndr) f (map Left valargs)
  
 --- A single alt case must be a selector. This means thee scrutinee is a simple
 +-- A single alt case must be a selector. This means the scrutinee is a simple
  -- variable, the alternative is a dataalt with a single non-wild binder that
  -- is also returned.
  mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) b ty [alt])) 
@@@ -881,7 -881,7 +881,7 @@@ genBlockRAM' (Left res) f args@[data_in
          wform       = AST.Wform [AST.WformElem data_in Nothing]
          ramassign      = AST.SigAssign ramloc wform
          rising_edge_clk = genExprFCall rising_edge (AST.PrimName $ AST.NSimple clockId)
-         statement   = AST.IfSm (AST.And rising_edge_clk (wrenable AST.:=: AST.PrimLit "'1'")) [ramassign] [] Nothing
+         statement   = AST.IfSm (AST.And rising_edge_clk wrenable) [ramassign] [] Nothing
  
  -----------------------------------------------------------------------------
  -- Function to generate VHDL for applications