We now output VHDL types in the correct order
authorChristiaan Baaij <christiaan.baaij@gmail.com>
Thu, 2 Jul 2009 14:44:58 +0000 (16:44 +0200)
committerChristiaan Baaij <christiaan.baaij@gmail.com>
Thu, 2 Jul 2009 14:44:58 +0000 (16:44 +0200)

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