Further reduce main and add a makeVHDL function.

diff --git a/Translator.hs b/Translator.hs
index 98380606884c24ba953a07216d1bb788d1747d22..ddd09fc340da9a401a24e1399c797de60c238234 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -42,10 +42,14 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
+  makeVHDL "Alu.hs" "salu"
+
+makeVHDL :: String -> String -> IO ()
+makeVHDL filename name = do
   -- Load the module
-  core <- loadModule "Alu.hs"
+  core <- loadModule filename
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["salu"]
+  vhdl <- moduleToVHDL core [name]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"