Add another higher order testcase, highordtest2.

This testcase can be succesfully normalized and translated to VHDL.

diff --git a/Adders.hs b/Adders.hs
index 2ee1de69534f144ab6f41d627fdfc7ce950e4f05..d4dbbf8c99d851b5c7cf7b49222ca994b42c8878 100644 (file)
--- a/Adders.hs
+++ b/Adders.hs
@@ -165,6 +165,16 @@ highordtest = \x ->
              in
                 \c d -> op' d c
 
+highordtest2 = \a b ->
+         case a of
+           High -> \c d -> d
+           Low -> let
+             op' :: Bit -> Bit -> Bit
+             op' = case b of
+                High -> \c d -> d
+                Low -> \c d -> c
+             in
+                \c d -> op' d c
 -- Four bit adder, using the continous adder below
 -- [a] -> [b] -> ([s], cout)
 --con_adder_4 as bs = 

diff --git a/Translator.hs b/Translator.hs
index 3f60330b37a68b8680cdedec20996f28134c5a42..7b548e7c8d67bb63da79dffe3bfa6dbe91ed814d 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -53,7 +53,7 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
-  makeVHDL "Adders.hs" "highordtest" True
+  makeVHDL "Adders.hs" "highordtest2" True
 
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do