Merge branch 'master' of git://github.com/christiaanb/clash into cλash

* 'master' of git://github.com/christiaanb/clash:
  Fix builtin functions (!),take and RangedWord

Conflicts:
	cλash/CLasH/VHDL/Generate.hs

diff --cc cλash/CLasH/VHDL/Generate.hs
index aca4e9570ff0e23dceaf7e7c1c1bf38b9200544e,5618532c2f1771fd18d88ba417120072e94206fb..5360cff1234cc226039dc2a25881bf7aa7e8b9ea
--- 1/cλash/CLasH/VHDL/Generate.hs
--- 2/cλash/CLasH/VHDL/Generate.hs
+++ b/cλash/CLasH/VHDL/Generate.hs
@@@ -313,12 -146,17 +313,17 @@@ genFromInteger' (Left res) f lits = do 
          ; (tycon, args) = Type.splitTyConApp ty
          ; name = Name.getOccString (TyCon.tyConName tycon)
          } ;
-   ; len <- case name of
-     "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
-     "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
-   ; let fname = case name of "SizedInt" -> toSignedId ; "SizedWord" -> toUnsignedId
-   ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname)) 
-             [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
+   ; case name of
+     "RangedWord" -> return $ AST.PrimLit (show (last lits))
+     otherwise -> do {
+       ; len <- case name of
 -        "SizedInt" -> MonadState.lift vsType $ tfp_to_int (sized_int_len_ty ty)
 -        "SizedWord" -> MonadState.lift vsType $ tfp_to_int (sized_word_len_ty ty)
 -        "RangedWord" -> MonadState.lift vsType $ tfp_to_int (ranged_word_bound_ty ty)
++        "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
++        "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
++        "RangedWord" -> MonadState.lift tsType $ tfp_to_int (ranged_word_bound_ty ty)
+       ; let fname = case name of "SizedInt" -> toSignedId ; "SizedWord" -> toUnsignedId
+       ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname))
+                 [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
+       }
    }
  
  genFromInteger' (Right name) _ _ = error $ "\nGenerate.genFromInteger': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
@@@ -1276,5 -1110,6 +1295,6 @@@ globalNameTable = Map.fromLis
    , (fromIntegerId    , (1, genFromInteger          ) )
    , (resizeId         , (1, genResize               ) )
    , (sizedIntId       , (1, genSizedInt             ) )
 -  , (tfvecId          , (1, genTFVec                ) )
 +  --, (tfvecId          , (1, genTFVec                ) )
+   , (minimumId        , (2, error $ "\nFunction name: \"minimum\" is used internally, use another name"))
    ]