Always use everything declared in VHDL work library

diff --git a/VHDL.hs b/VHDL.hs
index 8d36af75162a6bf4a8344a176993a15f643e0a90..1f08abe1016b9b251a84b0eb27cbb29d60e3cf15 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -63,7 +63,8 @@ createDesignFiles binds =
       ]
     full_context =
       mkUseAll ["work", "types"]
-      : ieee_context
+      : (mkUseAll ["work"]
+      : ieee_context)
     type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ vec_decls ++ ty_decls ++ subProgSpecs)
     type_package_body = AST.LUPackageBody $ AST.PackageBody typesId (concat tyfun_decls)
     subProgSpecs = concat (map subProgSpec tyfun_decls)