Remove createEntity from the VHDLState monad.

diff --git a/Translator.hs b/Translator.hs
index 5e36b3856b631666cc4fb62fb932631e21a33943..6a784251d3c310240fc657b8a0c183980cc80202 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -92,7 +92,7 @@ moduleToVHDL core list = do
       -- Create entities and architectures for them
       Monad.zipWithM processBind statefuls binds
       modFuncs nameFlatFunction
-      modFuncs VHDL.createEntity
+      modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdata {funcEntity = VHDL.createEntity hsfunc fdata})
       modFuncs VHDL.createArchitecture
       funcs <- getFuncs
       return $ VHDL.getDesignFiles (map snd funcs)

diff --git a/VHDL.hs b/VHDL.hs
index d9dce9e699f9188dfefc9726f625a7369bc7cd29..6f3705e421d6f0d55b16faef97054ac3f3462367 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -38,13 +38,12 @@ getDesignFiles funcs =
 createEntity ::
   HsFunction        -- | The function signature
   -> FuncData       -- | The function data collected so far
-  -> VHDLState ()
+  -> Maybe Entity   -- | The resulting entity
 
 createEntity hsfunc fdata = 
-  let func = flatFunc fdata in
-  case func of
+  case flatFunc fdata of
     -- Skip (builtin) functions without a FlatFunction
-    Nothing -> do return ()
+    Nothing -> Nothing
     -- Create an entity for all other functions
     Just flatfunc ->
       let 
@@ -60,9 +59,8 @@ createEntity hsfunc fdata =
           then Nothing
           else Just $ AST.PackageDec pkg_id (map AST.PDITD $ ty_decls ++ ty_decls')
         AST.EntityDec entity_id _ = ent_decl' 
-        entity' = Entity entity_id args' res' (Just ent_decl') pkg_decl
-      in do
-        setEntity hsfunc entity'
+      in 
+        Just $ Entity entity_id args' res' (Just ent_decl') pkg_decl
   where
     mkMap :: 
       [(SignalId, SignalInfo)]