Ignore cast expressions when generating VHDL.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 23 Jun 2009 12:54:24 +0000 (14:54 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 23 Jun 2009 12:54:24 +0000 (14:54 +0200)

No differences found