Always add a clk port map on instantiations.

This changes make the translator generate synthesizable VHDL again.

diff --git a/VHDL.hs b/VHDL.hs
index 00b5ddae2a3633e233aad4d6fe0e91235a13c005..4f8d1055af2e0df5a9db8b82ad7a709505a4e216 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -313,8 +313,9 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do
         label = "comp_ins_" ++ bndrToString bndr
         -- Add a clk port if we have state
         --clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
+        clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
         --portmaps = mkAssocElems sigs args res signature ++ (if hasState hsfunc then [clk_port] else [])
-        portmaps = mkAssocElems args bndr signature
+        portmaps = clk_port : mkAssocElems args bndr signature
         in
           return [AST.CSISm $ AST.CompInsSm (mkVHDLExtId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)]
     details -> error $ "Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details