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Always add a clk port map on instantiations.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 23 Jun 2009 10:53:47 +0000 (12:53 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 23 Jun 2009 10:53:47 +0000 (12:53 +0200)
This changes make the translator generate synthesizable VHDL again.


No differences found
The Cλash compiler