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Support VHDL generation for two-alternative cases.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 19 Jun 2009 10:39:44 +0000 (12:39 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 19 Jun 2009 10:39:44 +0000 (12:39 +0200)
This does not support single alternatives statements yet, and will never
support more than two alternatives. Only supports case statements on Bit
and Bool types for now.


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