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Don't generate ports for non-port signals.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 17 Feb 2009 16:36:27 +0000 (17:36 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 17 Feb 2009 16:37:30 +0000 (17:37 +0100)
This allows an entry in a VHDLSignalmap to be empty, which allows for
arguments and results that do not expand into a port, such as state.


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The Cλash compiler