Update outline.

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index 8b991c6bcd0eb3ffd85a9ef6fe797bee5d58ae44..074f6a6105a1ee1b20fa1944352d8f685b5717df 100644 (file)
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+++ b/Outline
@@ -1,46 +1,52 @@
-Context
-  Other FHDLs (short, Christiaan has details)
-
-  Advantages of clash / why clash?
-
-  VHDL / Verilog / EDIF etc. Why VHDL?
+Introduction
+*       Goals
+*       Outline
 
+*Context
+*       Other FHDLs (short, Christiaan has details)
+*       Advantages of clash / why clash?
 
 Haskell as hardware
-        Simple function -> component interpretation (Model: Structure)
-        Model: State
-          Explicit vs implicit passing of state (e.g, delay)
-          Explicit vs implicit marking
-        Interpret: Polymorphism
-        Interpret: Higher order
+*       Simple function -> component interpretation (Model: Structure)
+*       Partial application
+*       Model: State
+*         Explicit vs implicit passing of state (e.g, delay)
+*         Explicit vs implicit marking
+*       Interpret: Polymorphism
+*       Interpret: Higher order
        Need: Dependent types
+*       Recursion
        Impossible things: Infinite recursion, higher order expressions,
-        recursive types.
+                           recursive types, ...
 
 Prototype
-        Choice of Haskell
-        Core - description of the language (appendix?)
-       Stages (-> Core, Normalization, -> VHDL)
-        Implementation issues
+*       Choice of Haskell
+        VHDL / Verilog / EDIF etc. Why VHDL?
+*      Stages (-> Core, Normalization, -> VHDL)
+.       Core - description of the language (appendix?)
+        Implementation issues -- Which?
+        State annotations
 
         Haskell language coverage / constraints
                 Recursion
                 Builtin types
                 Custom types (Sum types, product types)
                 Function types / higher order expressions
+                State type -> Anything representable
 
 Normalization
-       Normal form
-       Rules used
-       Completeness / conditions on input
-       Termination
+*      Normal form
+*      Rules used
+.      Properties / Proofs (termination, soundness, completeness, determinism)
        Casts / Strictness / Casebinders not fully supported
 
 Future work
-       Boilerplate reduction (State distribution & pipelining)
-       Recursion
-        Multiple time domains (Events) -- Also, clock line optimization /
+.      Boilerplate reduction (State distribution & pipelining)
+*      Recursion
+*       Multiple time domains (Events) -- Also, clock line optimization /
                                        -- write enable
-       Multiple cycle descriptions
-        Higher order state
-        New language
+*      Multiple cycle descriptions
+*       Higher order state
+*       New language
+
+TODO: Define user / developer