tyfun_decls = Map.elems (final_session ^.vsTypeFuns)
ty_decls = map mktydecl $ Map.elems (final_session ^. vsTypes)
vec_decls = map (\(v_id, v_def) -> AST.PDITD $ AST.TypeDec v_id v_def) (Map.elems (final_session ^. vsElemTypes))
+ tfvec_index_decl = AST.PDISD $ AST.SubtypeDec tfvec_indexTM tfvec_index_def
+ tfvec_range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit "-1") (AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerTM) highId Nothing)
+ tfvec_index_def = AST.SubtypeIn integerTM (Just tfvec_range)
ieee_context = [
AST.Library $ mkVHDLBasicId "IEEE",
mkUseAll ["IEEE", "std_logic_1164"],
full_context =
mkUseAll ["work", "types"]
: ieee_context
- type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") (vec_decls ++ ty_decls ++ subProgSpecs)
+ type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ vec_decls ++ ty_decls ++ subProgSpecs)
type_package_body = AST.LUPackageBody $ AST.PackageBody typesId (concat tyfun_decls)
subProgSpecs = concat (map subProgSpec tyfun_decls)
subProgSpec = map (\(AST.SubProgBody spec _ _) -> AST.PDISS spec)
sig_dec_maybes <- mapM (mkSigDec' . fst) (filter ((/=res).fst) binds)
let sig_decs = Maybe.catMaybes $ sig_dec_maybes
- statements <- Monad.mapM mkConcSm binds
+ statementss <- Monad.mapM mkConcSm binds
+ let statements = concat statementss
return $ AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
where
procs = map mkStateProcSm [] -- (makeStatePairs flatfunc)
-- | Transforms a core binding into a VHDL concurrent statement
mkConcSm ::
(CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
- -> VHDLState AST.ConcSm -- ^ The corresponding VHDL component instantiation.
+ -> VHDLState [AST.ConcSm] -- ^ The corresponding VHDL component instantiations.
mkConcSm (bndr, app@(CoreSyn.App _ _))= do
let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
--let valargs = filter isValArg args in
if all is_var valargs then do
labels <- getFieldLabels (CoreUtils.exprType app)
- let assigns = zipWith mkassign labels valargs
- let block_id = bndrToVHDLId bndr
- let block = AST.BlockSm block_id [] (AST.PMapAspect []) [] assigns
- return $ AST.CSBSm block
+ return $ zipWith mkassign labels valargs
else
error $ "VHDL.mkConcSm Not in normal form: One ore more complex arguments: " ++ pprString args
where
dst_name = AST.NSimple (mkVHDLExtId (bndrToString bndr))
assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
in
- return $ AST.CSSASm assign
+ return [AST.CSSASm assign]
else
error $ "VHDL.mkConcSm Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ pprString valargs
Nothing -> error $ "Using function from another module that is not a known builtin: " ++ pprString f
(error $ "Using function '" ++ (bndrToString f) ++ "' without signature? This should not happen!")
(Map.lookup f signatures)
entity_id = ent_id signature
- label = bndrToString bndr
+ label = "comp_ins_" ++ bndrToString bndr
-- Add a clk port if we have state
--clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
+ clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
--portmaps = mkAssocElems sigs args res signature ++ (if hasState hsfunc then [clk_port] else [])
- portmaps = mkAssocElems args bndr signature
+ portmaps = clk_port : mkAssocElems args bndr signature
in
- return $ AST.CSISm $ AST.CompInsSm (mkVHDLExtId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
+ return [AST.CSISm $ AST.CompInsSm (mkVHDLExtId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)]
details -> error $ "Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
--- GHC generates some funny "r = r" bindings in let statements before
--- simplification. This outputs some dummy ConcSM for these, so things will at
--- least compile for now.
-mkConcSm (bndr, CoreSyn.Var _) = return $ AST.CSPSm $ AST.ProcSm (mkVHDLBasicId "unused") [] []
-
-- A single alt case must be a selector. This means thee scrutinee is a simple
-- variable, the alternative is a dataalt with a single non-wild binder that
-- is also returned.
let label = labels!!i
let sel_name = mkSelectedName scrut label
let sel_expr = AST.PrimName sel_name
- return $ mkUncondAssign (Left bndr) sel_expr
+ return [mkUncondAssign (Left bndr) sel_expr]
Nothing -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
_ -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
true_expr = (varToVHDLExpr true)
false_expr = (varToVHDLExpr false)
in
- return $ mkCondAssign (Left bndr) cond_expr true_expr false_expr
+ return [mkCondAssign (Left bndr) cond_expr true_expr false_expr]
mkConcSm (_, (Case (Var _) _ _ alts)) = error "VHDL.mkConcSm Not in normal form: Case statement with more than two alternatives"
mkConcSm (_, Case _ _ _ _) = error "VHDL.mkConcSm Not in normal form: Case statement has does not have a simple variable as scrutinee"
mkConcSm (bndr, expr) = error $ "VHDL.mkConcSM Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
let name = Name.getOccString (TyCon.tyConName tycon)
case name of
"TFVec" -> do
- res <- mk_vector_ty (tfvec_len ty) (tfvec_elem ty) ty
+ res <- mk_vector_ty (tfvec_len ty) (tfvec_elem ty)
return $ Just $ (Arrow.second Right) res
-- "SizedWord" -> do
-- res <- mk_vector_ty (sized_word_len ty) ty
-- return $ Just $ (Arrow.second Left) res
"RangedWord" -> do
- res <- mk_natural_ty 0 (ranged_word_bound ty) ty
+ res <- mk_natural_ty 0 (ranged_word_bound ty)
return $ Just $ (Arrow.second Right) res
-- Create a custom type from this tycon
otherwise -> mk_tycon_ty tycon args
mk_vector_ty ::
Int -- ^ The length of the vector
-> Type.Type -- ^ The Haskell element type of the Vector
- -> Type.Type -- ^ The Haskell type to create a VHDL type for
-> VHDLState (AST.TypeMark, AST.SubtypeIn) -- The typemark created.
- mk_vector_ty len el_ty ty = do
+ mk_vector_ty len el_ty = do
elem_types_map <- getA vsElemTypes
el_ty_tm <- vhdl_ty el_ty
let ty_id = mkVHDLExtId $ "vector-"++ (AST.fromVHDLId el_ty_tm) ++ "-0_to_" ++ (show len)
return (ty_id, ty_def)
Nothing -> do
let vec_id = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId el_ty_tm)
- let vec_def = AST.TDA $ AST.UnconsArrayDef [naturalTM] el_ty_tm
+ let vec_def = AST.TDA $ AST.UnconsArrayDef [tfvec_indexTM] el_ty_tm
modA vsElemTypes (Map.insert (OrdType el_ty) (vec_id, vec_def))
- modA vsTypeFuns (Map.insert (OrdType ty) (genUnconsVectorFuns el_ty_tm vec_id))
+ modA vsTypeFuns (Map.insert (OrdType el_ty) (genUnconsVectorFuns el_ty_tm vec_id))
let ty_def = AST.SubtypeIn vec_id (Just range)
return (ty_id, ty_def)
mk_natural_ty ::
Int -- ^ The minimum bound (> 0)
-> Int -- ^ The maximum bound (> minimum bound)
- -> Type.Type -- ^ The Haskell type to create a VHDL type for
-> VHDLState (AST.TypeMark, AST.SubtypeIn) -- The typemark created.
- mk_natural_ty min_bound max_bound ty = do
+ mk_natural_ty min_bound max_bound = do
let ty_id = mkVHDLExtId $ "nat_" ++ (show min_bound) ++ "_to_" ++ (show max_bound)
let range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit $ (show min_bound)) (AST.PrimLit $ (show max_bound))
let ty_def = AST.SubtypeIn naturalTM (Just range)
return (ty_id, ty_def)
-
-
+
builtin_types =
Map.fromList [
("Bit", std_logic_ty),
projects / matthijs / master-project / cλash.git / commitdiff