Generate VHDL for UncondDefs.

diff --git a/VHDL.hs b/VHDL.hs
index c791a34da6bedc2061dad4041f94dc2ce23df924..adf1bf9694faa073f4944dd7c157254c7cb224de 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -192,6 +192,14 @@ mkConcSm sigs (FApp hsfunc args res) = do
   let portmaps = mkAssocElems sigs args res entity
   return $ AST.CSISm $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
 
+mkConcSm sigs (UncondDef src dst) = do
+  let src_name  = AST.NSimple (getSignalId $ signalInfo sigs src)
+  let src_expr  = AST.PrimName src_name
+  let src_wform = AST.Wform [AST.WformElem src_expr Nothing]
+  let dst_name  = AST.NSimple (getSignalId $ signalInfo sigs dst)
+  let assign    = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
+  return $ AST.CSSASm assign
+
 mkAssocElems :: 
   [(SignalId, SignalInfo)]      -- | The signals in the current architecture
   -> [SignalMap]                -- | The signals that are applied to function