Map the clk port on stateful function applications.

diff --git a/VHDL.hs b/VHDL.hs
index 80b069be1dca016621384dbda3c91507a991d8f7..b448672131c980bbe0df173fe86938235ce50ea7 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -203,7 +203,9 @@ mkConcSm sigs (FApp hsfunc args res) = do
         (funcEntity fdata)
   let entity_id = ent_id entity
   label <- uniqueName (AST.fromVHDLId entity_id)
-  let portmaps = mkAssocElems sigs args res entity
+  -- Add a clk port if we have state
+  let clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLId "clk") "clk"
+  let portmaps = mkAssocElems sigs args res entity ++ (if hasState hsfunc then [clk_port] else [])
   return $ AST.CSISm $ AST.CompInsSm (mkVHDLId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
 
 mkConcSm sigs (UncondDef src dst) = do