import CLasH.HardwareTypes
import CLasH.Translator.Annotations
-constant :: NaturalT n => e -> Op n e
-constant e a b = copy e
-
-invop :: Op n Bit
-invop a b = map hwnot a
-
-andop :: (e -> e -> e) -> Op n e
-andop f a b = zipWith f a b
-
--- Is any bit set?
---anyset :: (PositiveT n) => Op n Bit
-anyset :: NaturalT n => (e -> e -> e) -> e -> Op n e
---anyset a b = copy undefined (a' `hwor` b')
-anyset f s a b = constant (f a' b') a b
- where
- a' = foldl f s a
- b' = foldl f s b
-
-xhwor = hwor
-
-type Op n e = (Vector n e -> Vector n e -> Vector n e)
-type Opcode = Bit
+import HighOrdAluOps
{-# ANN sim_input TestInput#-}
sim_input :: [(Opcode, Vector D4 (SizedInt D8), Vector D4 (SizedInt D8))]
--- /dev/null
+module HighOrdAluOps where
+
+import qualified Prelude as P
+import CLasH.HardwareTypes
+import CLasH.Translator.Annotations
+
+constant :: NaturalT n => e -> Op n e
+constant e a b = copy e
+
+invop :: Op n Bit
+invop a b = map hwnot a
+
+andop :: (e -> e -> e) -> Op n e
+andop f a b = zipWith f a b
+
+-- Is any bit set?
+--anyset :: (PositiveT n) => Op n Bit
+anyset :: NaturalT n => (e -> e -> e) -> e -> Op n e
+--anyset a b = copy undefined (a' `hwor` b')
+anyset f s a b = constant (f a' b') a b
+ where
+ a' = foldl f s a
+ b' = foldl f s b
+
+xhwor = hwor
+
+type Op n e = (Vector n e -> Vector n e -> Vector n e)
+type Opcode = Bit
\ No newline at end of file
-- Translate to VHDL
vhdl <- moduleToVHDL env cores specs
-- Write VHDL to file. Just use the first entity for the name
- let top_entity = (\(t, _, _) -> t) $ head specs
+ let top_entity = head $ Maybe.catMaybes $ map (\(t, _, _) -> t) specs
let dir = "./vhdl/" ++ (show top_entity) ++ "/"
prepareDir dir
mapM (writeVHDL dir) vhdl
-- Store the bindings we loaded
tsBindings %= Map.fromList all_bindings
test_binds <- catMaybesM $ Monad.mapM mkTest specs
- let topbinds = map (\(top, _, _) -> top) specs
- createDesignFiles (topbinds ++ test_binds)
+ let topbinds = Maybe.catMaybes $ map (\(top, _, _) -> top) specs
+ case topbinds of
+ [] -> error $ "Could not find top entity requested"
+ tops -> createDesignFiles (tops ++ test_binds)
mapM (putStr . render . Ppr.ppr . snd) vhdl
return vhdl
where
mkTest :: EntitySpec -> TranslatorSession (Maybe CoreSyn.CoreBndr)
-- Create a testbench for any entry that has test input
mkTest (_, _, Nothing) = return Nothing
- mkTest (top, _, Just input) = do
+ mkTest (Nothing, _, _) = return Nothing
+ mkTest (Just top, _, Just input) = do
bndr <- createTestbench Nothing cores input top
return $ Just bndr
-- | A specification of an entity we can generate VHDL for. Consists of the
-- binder of the top level entity, an optional initial state and an optional
-- test input.
-type EntitySpec = (CoreSyn.CoreBndr, Maybe CoreSyn.CoreExpr, Maybe CoreSyn.CoreExpr)
+type EntitySpec = (Maybe CoreSyn.CoreBndr, Maybe CoreSyn.CoreExpr, Maybe CoreSyn.CoreExpr)
-- | A function that knows which parts of a module to compile
type Finder =
top <- findBind topc mod
state <- findExpr statec mod
test <- findExpr testc mod
- case top of
- Just t -> return [(t, state, test)]
- Nothing -> error $ "Could not find top entity requested"
+ return [(top, state, test)]
+ -- case top of
+ -- Just t -> return [(t, state, test)]
+ -- Nothing -> return error $ "Could not find top entity requested"