Add port declarations to the VHDL entities.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 13:07:06 +0000 (14:07 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 13:07:06 +0000 (14:07 +0100)

No differences found