Remove a few stale TODOs.

diff --git a/Translator.hs b/Translator.hs
index a94e3f44c39d0a7b8fcdbc99c232e76f52ef0bfa..92251eede3caf0dde2915ae9cf006f9078ce638f 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -272,7 +272,6 @@ resolvFunc hsfunc = do
   -- when it is a builtin function.
   Monad.unless (Map.member hsfunc flatfuncmap) $ do
   Monad.unless (elem hsfunc VHDL.builtin_hsfuncs) $ do
-  -- TODO: Builtin functions
   -- New function, resolve it
   core <- getA tsCoreModule
   -- Find the named function

diff --git a/VHDL.hs b/VHDL.hs
index 4d8b6669d69503a7f8977eaac1996488648a9ccd..572e221b4abb120e94d4871489e5f94b92f1be81 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -35,7 +35,6 @@ createDesignFiles ::
   -> [(AST.VHDLId, AST.DesignFile)]
 
 createDesignFiles flatfuncmap =
-  -- TODO: Output types
   (mkVHDLId "types", AST.DesignFile ieee_context [type_package]) :
   map (Arrow.second $ AST.DesignFile full_context) units
   
@@ -171,8 +170,6 @@ createArchitecture hsfunc flatfunc = do
     args = flat_args flatfunc
     res  = flat_res  flatfunc
     defs = flat_defs flatfunc
-    -- TODO: Unique ty_decls
-    -- TODO: Store ty_decls somewhere
     procs = map mkStateProcSm (makeStatePairs flatfunc)
     procs' = map AST.CSPSm procs
     -- mkSigDec only uses vsTypes from the state