Added main function to Main module

diff --git a/Main.hs b/Main.hs
index 078f46fe0807d2d902c332c3adb028ad3d47b579..42818c0c26b986a514f4246d208337b6e8aa9d92 100644 (file)
--- a/Main.hs
+++ b/Main.hs
@@ -3,4 +3,4 @@ module Main where
 import Translator
 
 main = do
-  makeVHDL "Adders.hs" "functiontest" True
\ No newline at end of file
+  makeVHDL "Adders.hs" "highordtest2" True
\ No newline at end of file

diff --git a/Translator.hs b/Translator.hs
index 1786332678717097892bd84c7b2ac66c0badefba..6b0cdd1e06c298e4a8261cb707274e1e9bd3ab7d 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -52,9 +52,6 @@ import FlattenTypes
 import VHDLTypes
 import qualified VHDL
 
-main = do
-  makeVHDL "Adders.hs" "highordtest2" True
-
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do
   -- Load the module