Update outline.

diff --git a/Outline b/Outline
index 73246f9dc78177926933e61cfeb46677cee82dea..0825321c66cf5b6bd53a1aa0a4c240cee33bf9c7 100644 (file)
--- a/Outline
+++ b/Outline
@@ -1,13 +1,32 @@
-Implementation issues
+Context
+  Other FHDLs (short, Christiaan has details)
+
+  Advantages of clash / why clash?
+
+  VHDL / Verilog / EDIF etc. Why VHDL?
 
-State
+
+Haskell as hardware
+        Simple function -> component interpretation (Model: Structure)
+        Model: State
+          Explicit vs implicit passing of state (e.g, delay)
+          Explicit vs implicit marking
+        Interpret: Polymorphism
+        Interpret: Higher order
+       Need: Dependent types
+       Impossible things: Infinite recursion, higher order expressions
 
 Prototype
+        Choice of Haskell
+        Core - description of the language (appendix?)
        Stages (-> Core, Normalization, -> VHDL)
+        Implementation issues
 
-Core
-
-VHDL vs EDIF generation
+        Haskell language coverage / constraints
+                Recursion
+                Builtin types
+                Custom types (Sum types, product types)
+                Function types / higher order expressions
 
 Normalization
        Normal form
@@ -16,26 +35,9 @@ Normalization
        Termination
        Casts
 
-Context
-
-Other FHDLs
-
-VHDL / Verilog / EDIF etc.
-
-Advantages of clash / why clash?
-
-Haskell as hardware
-       Dependent types
-       Impossible things: Infinite recursion, higher order expressions
-
-Haskell language coverage / constraints
-       Recursion
-       Builtin types
-       Custom types (Sum types, product types)
-       Function types / higher order expressions
-
 Future work
        Boilerplate reduction (State distribution & pipelining)
        Recursion
-       Multiple time domains
+       Multiple time domains (Events)
        Multiple cycle descriptions
+        Higher order state