Prepend "comp_ins_" to component instantiation labels.

This should ensure that these labels are fairly unique (no guarantees yet,
though).

diff --git a/VHDL.hs b/VHDL.hs
index 3eddd8bfb66860a2271a9b081377bbf6254b78c6..00b5ddae2a3633e233aad4d6fe0e91235a13c005 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -310,7 +310,7 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do
           (error $ "Using function '" ++ (bndrToString f) ++ "' without signature? This should not happen!") 
           (Map.lookup f signatures)
         entity_id = ent_id signature
-        label = bndrToString bndr
+        label = "comp_ins_" ++ bndrToString bndr
         -- Add a clk port if we have state
         --clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
         --portmaps = mkAssocElems sigs args res signature ++ (if hasState hsfunc then [clk_port] else [])